upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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71 lines
1.6 KiB
71 lines
1.6 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2014 Google, Inc
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* Written by Simon Glass <sjg@chromium.org>
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*/
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#include <common.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <inttypes.h>
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#include <pci.h>
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static int sandbox_pci_write_config(struct udevice *bus, pci_dev_t devfn,
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uint offset, ulong value,
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enum pci_size_t size)
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{
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struct dm_pci_emul_ops *ops;
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struct udevice *emul;
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int ret;
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ret = sandbox_pci_get_emul(bus, devfn, &emul);
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if (ret)
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return ret == -ENODEV ? 0 : ret;
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ops = pci_get_emul_ops(emul);
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if (!ops || !ops->write_config)
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return -ENOSYS;
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return ops->write_config(emul, offset, value, size);
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}
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static int sandbox_pci_read_config(struct udevice *bus, pci_dev_t devfn,
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uint offset, ulong *valuep,
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enum pci_size_t size)
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{
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struct dm_pci_emul_ops *ops;
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struct udevice *emul;
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int ret;
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/* Prepare the default response */
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*valuep = pci_get_ff(size);
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ret = sandbox_pci_get_emul(bus, devfn, &emul);
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if (ret)
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return ret == -ENODEV ? 0 : ret;
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ops = pci_get_emul_ops(emul);
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if (!ops || !ops->read_config)
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return -ENOSYS;
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return ops->read_config(emul, offset, valuep, size);
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}
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static const struct dm_pci_ops sandbox_pci_ops = {
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.read_config = sandbox_pci_read_config,
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.write_config = sandbox_pci_write_config,
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};
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static const struct udevice_id sandbox_pci_ids[] = {
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{ .compatible = "sandbox,pci" },
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{ }
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};
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U_BOOT_DRIVER(pci_sandbox) = {
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.name = "pci_sandbox",
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.id = UCLASS_PCI,
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.of_match = sandbox_pci_ids,
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.ops = &sandbox_pci_ops,
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/* Attach an emulator if we can */
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.child_post_bind = dm_scan_fdt_dev,
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.per_child_platdata_auto_alloc_size =
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sizeof(struct pci_child_platdata),
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};
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