upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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426 lines
12 KiB
426 lines
12 KiB
/*
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* (C) Copyright 2006-2009
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* (C) Copyright 2006
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* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
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* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <asm/ppc4xx.h>
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#include <asm/ppc4xx-gpio.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/bitops.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if !defined(CONFIG_SYS_NO_FLASH)
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extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
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#endif
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extern void __ft_board_setup(void *blob, bd_t *bd);
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ulong flash_get_size(ulong base, int banknum);
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static inline u32 get_async_pci_freq(void)
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{
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if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) &
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CONFIG_SYS_BCSR5_PCI66EN)
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return 66666666;
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else
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return 33333333;
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}
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int board_early_init_f(void)
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{
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u32 sdr0_cust0;
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u32 sdr0_pfc1, sdr0_pfc2;
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u32 reg;
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mtdcr(EBC0_CFGADDR, EBC0_CFG);
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mtdcr(EBC0_CFGDATA, 0xb8400000);
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/*
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* Setup the interrupt controller polarities, triggers, etc.
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*/
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mtdcr(UIC0SR, 0xffffffff); /* clear all */
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mtdcr(UIC0ER, 0x00000000); /* disable all */
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mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
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mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */
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mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
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mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
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mtdcr(UIC0SR, 0xffffffff); /* clear all */
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mtdcr(UIC1SR, 0xffffffff); /* clear all */
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mtdcr(UIC1ER, 0x00000000); /* disable all */
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mtdcr(UIC1CR, 0x00000000); /* all non-critical */
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mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
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mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
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mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
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mtdcr(UIC1SR, 0xffffffff); /* clear all */
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mtdcr(UIC2SR, 0xffffffff); /* clear all */
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mtdcr(UIC2ER, 0x00000000); /* disable all */
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mtdcr(UIC2CR, 0x00000000); /* all non-critical */
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mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
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mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
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mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
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mtdcr(UIC2SR, 0xffffffff); /* clear all */
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/* Check and reconfigure the PCI sync clock if necessary */
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ppc4xx_pci_sync_clock_config(get_async_pci_freq());
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/* 50MHz tmrclk */
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out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x04, 0x00);
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/* clear write protects */
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out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x07, 0x00);
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/* enable Ethernet */
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out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x08, 0x00);
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/* enable USB device */
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out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x09, 0x20);
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/* select Ethernet (and optionally IIC1) pins */
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mfsdr(SDR0_PFC1, sdr0_pfc1);
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sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
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SDR0_PFC1_SELECT_CONFIG_4;
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#ifdef CONFIG_I2C_MULTI_BUS
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sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL);
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#endif
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/* Two UARTs, so we need 4-pin mode. Also, we want CTS/RTS mode. */
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sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
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sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_CTS_RTS;
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sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_CTS_RTS;
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mfsdr(SDR0_PFC2, sdr0_pfc2);
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sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
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SDR0_PFC2_SELECT_CONFIG_4;
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mtsdr(SDR0_PFC2, sdr0_pfc2);
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mtsdr(SDR0_PFC1, sdr0_pfc1);
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/* PCI arbiter enabled */
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mfsdr(SDR0_PCI0, reg);
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mtsdr(SDR0_PCI0, 0x80000000 | reg);
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/* setup NAND FLASH */
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mfsdr(SDR0_CUST0, sdr0_cust0);
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sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
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SDR0_CUST0_NDFC_ENABLE |
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SDR0_CUST0_NDFC_BW_8_BIT |
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SDR0_CUST0_NDFC_ARE_MASK |
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(0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
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mtsdr(SDR0_CUST0, sdr0_cust0);
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return 0;
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}
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int misc_init_r(void)
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{
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#if !defined(CONFIG_SYS_NO_FLASH)
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uint pbcr;
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int size_val = 0;
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#endif
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#ifdef CONFIG_440EPX
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unsigned long usb2d0cr = 0;
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unsigned long usb2phy0cr, usb2h0cr = 0;
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unsigned long sdr0_pfc1;
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char *act = getenv("usbact");
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#endif
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u32 reg;
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#if !defined(CONFIG_SYS_NO_FLASH)
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/* Re-do flash sizing to get full correct info */
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/* adjust flash start and offset */
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gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
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gd->bd->bi_flashoffset = 0;
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#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \
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defined(CONFIG_SYS_RAMBOOT)
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mtdcr(EBC0_CFGADDR, PB3CR);
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#else
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mtdcr(EBC0_CFGADDR, PB0CR);
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#endif
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pbcr = mfdcr(EBC0_CFGDATA);
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size_val = ffs(gd->bd->bi_flashsize) - 21;
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pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
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#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \
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defined(CONFIG_SYS_RAMBOOT)
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mtdcr(EBC0_CFGADDR, PB3CR);
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#else
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mtdcr(EBC0_CFGADDR, PB0CR);
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#endif
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mtdcr(EBC0_CFGDATA, pbcr);
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/*
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* Re-check to get correct base address
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*/
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flash_get_size(gd->bd->bi_flashstart, 0);
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#ifdef CONFIG_ENV_IS_IN_FLASH
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/* Monitor protection ON by default */
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(void)flash_protect(FLAG_PROTECT_SET,
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-CONFIG_SYS_MONITOR_LEN,
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0xffffffff,
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&flash_info[0]);
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/* Env protection ON by default */
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(void)flash_protect(FLAG_PROTECT_SET,
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CONFIG_ENV_ADDR_REDUND,
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CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
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&flash_info[0]);
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#endif
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#endif /* CONFIG_SYS_NO_FLASH */
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/*
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* USB suff...
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*/
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#ifdef CONFIG_440EPX
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if (act == NULL || strcmp(act, "hostdev") == 0) {
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/* SDR Setting */
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mfsdr(SDR0_PFC1, sdr0_pfc1);
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mfsdr(SDR0_USB2D0CR, usb2d0cr);
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mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
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mfsdr(SDR0_USB2H0CR, usb2h0cr);
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
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/*
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* An 8-bit/60MHz interface is the only possible alternative
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* when connecting the Device to the PHY
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*/
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usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
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usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
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/*
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* To enable the USB 2.0 Device function
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* through the UTMI interface
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*/
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usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
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usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;
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sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
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sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;
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mtsdr(SDR0_PFC1, sdr0_pfc1);
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mtsdr(SDR0_USB2D0CR, usb2d0cr);
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mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
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mtsdr(SDR0_USB2H0CR, usb2h0cr);
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/*clear resets*/
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udelay (1000);
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mtsdr(SDR0_SRST1, 0x00000000);
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udelay (1000);
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mtsdr(SDR0_SRST0, 0x00000000);
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printf("USB: Host(int phy) Device(ext phy)\n");
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} else if (strcmp(act, "dev") == 0) {
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/*-------------------PATCH-------------------------------*/
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mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
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mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
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udelay (1000);
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mtsdr(SDR0_SRST1, 0x672c6000);
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udelay (1000);
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mtsdr(SDR0_SRST0, 0x00000080);
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udelay (1000);
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mtsdr(SDR0_SRST1, 0x60206000);
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*(unsigned int *)(0xe0000350) = 0x00000001;
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udelay (1000);
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mtsdr(SDR0_SRST1, 0x60306000);
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/*-------------------PATCH-------------------------------*/
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/* SDR Setting */
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mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
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mfsdr(SDR0_USB2H0CR, usb2h0cr);
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mfsdr(SDR0_USB2D0CR, usb2d0cr);
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mfsdr(SDR0_PFC1, sdr0_pfc1);
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
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usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
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usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
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usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
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usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;
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sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
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sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
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mtsdr(SDR0_USB2H0CR, usb2h0cr);
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mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
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mtsdr(SDR0_USB2D0CR, usb2d0cr);
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mtsdr(SDR0_PFC1, sdr0_pfc1);
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/* clear resets */
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udelay (1000);
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mtsdr(SDR0_SRST1, 0x00000000);
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udelay (1000);
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mtsdr(SDR0_SRST0, 0x00000000);
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printf("USB: Device(int phy)\n");
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}
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#endif /* CONFIG_440EPX */
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mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */
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reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
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mtsdr(SDR0_SRST1, reg);
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/*
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* Clear PLB4A0_ACR[WRP]
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* This fix will make the MAL burst disabling patch for the Linux
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* EMAC driver obsolete.
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*/
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reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
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mtdcr(PLB4A0_ACR, reg);
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return 0;
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}
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int checkboard(void)
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{
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char *s = getenv("serial#");
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u8 rev;
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u32 clock = get_async_pci_freq();
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#ifdef CONFIG_440EPX
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printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board");
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#else
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printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
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#endif
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rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0));
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printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000);
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if (s != NULL) {
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puts(", serial# ");
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puts(s);
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}
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putc('\n');
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/*
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* Reconfiguration of the PCI sync clock is already done,
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* now check again if everything is in range:
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*/
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if (ppc4xx_pci_sync_clock_config(clock)) {
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printf("ERROR: PCI clocking incorrect (async=%d "
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"sync=%ld)!\n", clock, get_PCI_freq());
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}
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return (0);
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}
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#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
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/*
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* Assign interrupts to PCI devices.
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*/
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void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
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{
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pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2);
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}
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#endif
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#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)
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/*
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* On NAND-booting sequoia, we need to patch the chips select numbers
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* in the dtb (CS0 - NAND, CS3 - NOR)
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*/
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void ft_board_setup(void *blob, bd_t *bd)
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{
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int rc;
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int len;
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int nodeoffset;
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struct fdt_property *prop;
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u32 *reg;
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char path[32];
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/* First do common fdt setup */
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__ft_board_setup(blob, bd);
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/* And now configure NOR chip select to 3 instead of 0 */
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strcpy(path, "/plb/opb/ebc/nor_flash@0,0");
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nodeoffset = fdt_path_offset(blob, path);
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prop = fdt_get_property_w(blob, nodeoffset, "reg", &len);
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if (prop == NULL) {
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printf("Unable to update NOR chip select for NAND booting\n");
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return;
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}
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reg = (u32 *)&prop->data[0];
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reg[0] = 3;
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rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1);
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if (rc) {
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printf("Unable to update property NOR mappings, err=%s\n",
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fdt_strerror(rc));
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return;
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}
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/* And now configure NAND chip select to 0 instead of 3 */
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strcpy(path, "/plb/opb/ebc/ndfc@3,0");
|
|
nodeoffset = fdt_path_offset(blob, path);
|
|
prop = fdt_get_property_w(blob, nodeoffset, "reg", &len);
|
|
if (prop == NULL) {
|
|
printf("Unable to update NDFC chip select for NAND booting\n");
|
|
return;
|
|
}
|
|
reg = (u32 *)&prop->data[0];
|
|
reg[0] = 0;
|
|
rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1);
|
|
if (rc) {
|
|
printf("Unable to update property NDFC mappings, err=%s\n",
|
|
fdt_strerror(rc));
|
|
return;
|
|
}
|
|
}
|
|
#endif /* CONFIG_NAND_U_BOOT */
|
|
|