upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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128 lines
3.7 KiB
128 lines
3.7 KiB
/*
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* (C) Copyright 2001-2003
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <command.h>
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#include <malloc.h>
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DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f (void)
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{
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/*
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* IRQ 0-15 405GP internally generated; active high; level sensitive
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* IRQ 16 405GP internally generated; active low; level sensitive
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* IRQ 17-24 RESERVED
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* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
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* IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
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* IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
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* IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
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* IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
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* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
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* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
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*/
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
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mtdcr(uicer, 0x00000000); /* disable all ints */
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mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
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mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
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mtdcr(uictr, 0x10000000); /* set int trigger levels */
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mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
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/*
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* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
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*/
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mtebc (epcr, 0xa8400000); /* ebc always driven */
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/*
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* Reset CPLD via GPIO13 (CS4) pin
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*/
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out_be32((void *)GPIO0_OR,
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in_be32((void *)GPIO0_OR) & ~(0x80000000 >> 13));
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udelay(1000); /* wait 1ms */
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out_be32((void *)GPIO0_OR,
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in_be32((void *)GPIO0_OR) | (0x80000000 >> 13));
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udelay(1000); /* wait 1ms */
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return 0;
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}
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int misc_init_r (void)
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{
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/* adjust flash start and offset */
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gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
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gd->bd->bi_flashoffset = 0;
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return (0);
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}
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/*
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* Check Board Identity:
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*/
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int checkboard (void)
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{
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char str[64];
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int i = getenv_r ("serial#", str, sizeof(str));
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unsigned char trans[16] = {0x0,0x8,0x4,0xc,0x2,0xa,0x6,0xe,
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0x1,0x9,0x5,0xd,0x3,0xb,0x7,0xf};
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unsigned char id1, id2, rev;
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puts ("Board: ");
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if (i == -1)
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puts ("### No HW ID - assuming DP405");
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else
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puts(str);
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id1 = trans[(~(in_be32((void *)GPIO0_IR) >> 5)) & 0x0000000f];
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id2 = trans[(~(in_be32((void *)GPIO0_IR) >> 9)) & 0x0000000f];
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rev = in_8((void *)0xf0001000);
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if (rev & 0x10) /* old DP405 compatibility */
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rev = in_8((void *)0xf0000800);
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switch (rev & 0xc0) {
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case 0x00:
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puts(" (HW=DP405");
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break;
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case 0x80:
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puts(" (HW=DP405/CO");
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break;
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case 0xc0:
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puts(" (HW=DN405");
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break;
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}
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printf(", ID=0x%1X%1X, PLD=0x%02X", id2, id1, rev & 0x0f);
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if ((rev & 0xc0) == 0xc0) {
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printf(", C5V=%s",
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in_be32((void *)GPIO0_IR) & 0x40000000 ? "off" : "on");
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}
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puts(")\n");
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return 0;
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}
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