upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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130 lines
3.3 KiB
130 lines
3.3 KiB
/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
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*
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* (C) Copyright 2008
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* Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <s3c6400.h>
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/* ------------------------------------------------------------------------- */
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#define CS8900_Tacs 0x0 /* 0clk address set-up */
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#define CS8900_Tcos 0x4 /* 4clk chip selection set-up */
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#define CS8900_Tacc 0xE /* 14clk access cycle */
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#define CS8900_Tcoh 0x1 /* 1clk chip selection hold */
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#define CS8900_Tah 0x4 /* 4clk address holding time */
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#define CS8900_Tacp 0x6 /* 6clk page mode access cycle */
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#define CS8900_PMC 0x0 /* normal(1data)page mode configuration */
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static inline void delay(unsigned long loops)
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{
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__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
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"bne 1b"
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: "=r" (loops) : "0" (loops));
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}
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/*
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* Miscellaneous platform dependent initialisations
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*/
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static void cs8900_pre_init(void)
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{
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SROM_BW_REG &= ~(0xf << 4);
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SROM_BW_REG |= (1 << 7) | (1 << 6) | (1 << 4);
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SROM_BC1_REG = ((CS8900_Tacs << 28) + (CS8900_Tcos << 24) +
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(CS8900_Tacc << 16) + (CS8900_Tcoh << 12) +
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(CS8900_Tah << 8) + (CS8900_Tacp << 4) + CS8900_PMC);
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}
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int board_init(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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cs8900_pre_init();
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/* NOR-flash in SROM0 */
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/* Enable WAIT */
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SROM_BW_REG |= 4 | 8 | 1;
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gd->bd->bi_arch_number = MACH_TYPE;
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
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return 0;
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}
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int dram_init(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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return 0;
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}
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#ifdef CONFIG_DISPLAY_BOARDINFO
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int checkboard(void)
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{
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printf("Board: SMDK6400\n");
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return 0;
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}
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#endif
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#ifdef CONFIG_ENABLE_MMU
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ulong virt_to_phy_smdk6400(ulong addr)
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{
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if ((0xc0000000 <= addr) && (addr < 0xc8000000))
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return addr - 0xc0000000 + 0x50000000;
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else
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printf("do not support this address : %08lx\n", addr);
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return addr;
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}
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#endif
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#if defined(CONFIG_CMD_NAND) && defined(CONFIG_SYS_NAND_LEGACY)
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#include <linux/mtd/nand.h>
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extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
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void nand_init(void)
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{
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nand_probe(CONFIG_SYS_NAND_BASE);
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if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN)
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print_size(nand_dev_desc[0].totlen, "\n");
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}
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#endif
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ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t *info)
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{
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if (banknum == 0) { /* non-CFI boot flash */
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info->portwidth = FLASH_CFI_16BIT;
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info->chipwidth = FLASH_CFI_BY16;
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info->interface = FLASH_CFI_X16;
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return 1;
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} else
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return 0;
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}
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