upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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331 lines
7.5 KiB
331 lines
7.5 KiB
/*
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* Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
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* Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <div64.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#ifdef CONFIG_MXC_MMC
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#include <asm/arch/mxcmmc.h>
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#endif
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/*
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* get the system pll clock in Hz
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*
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* mfi + mfn / (mfd +1)
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* f = 2 * f_ref * --------------------
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* pd + 1
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*/
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unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
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{
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unsigned int mfi = (pll >> 10) & 0xf;
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unsigned int mfn = pll & 0x3ff;
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unsigned int mfd = (pll >> 16) & 0x3ff;
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unsigned int pd = (pll >> 26) & 0xf;
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mfi = mfi <= 5 ? 5 : mfi;
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return lldiv(2 * (u64)f_ref * (mfi * (mfd + 1) + mfn),
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(mfd + 1) * (pd + 1));
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}
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static ulong clk_in_32k(void)
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{
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return 1024 * CONFIG_MX27_CLK32;
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}
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static ulong clk_in_26m(void)
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{
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struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
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if (readl(&pll->cscr) & CSCR_OSC26M_DIV1P5) {
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/* divide by 1.5 */
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return 26000000 * 2 / 3;
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} else {
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return 26000000;
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}
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}
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ulong imx_get_mpllclk(void)
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{
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struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
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ulong cscr = readl(&pll->cscr);
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ulong fref;
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if (cscr & CSCR_MCU_SEL)
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fref = clk_in_26m();
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else
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fref = clk_in_32k();
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return imx_decode_pll(readl(&pll->mpctl0), fref);
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}
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ulong imx_get_armclk(void)
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{
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struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
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ulong cscr = readl(&pll->cscr);
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ulong fref = imx_get_mpllclk();
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ulong div;
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if (!(cscr & CSCR_ARM_SRC_MPLL))
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fref = lldiv((fref * 2), 3);
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div = ((cscr >> 12) & 0x3) + 1;
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return lldiv(fref, div);
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}
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ulong imx_get_ahbclk(void)
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{
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struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
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ulong cscr = readl(&pll->cscr);
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ulong fref = imx_get_mpllclk();
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ulong div;
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div = ((cscr >> 8) & 0x3) + 1;
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return lldiv(fref * 2, 3 * div);
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}
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ulong imx_get_spllclk(void)
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{
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struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
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ulong cscr = readl(&pll->cscr);
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ulong fref;
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if (cscr & CSCR_SP_SEL)
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fref = clk_in_26m();
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else
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fref = clk_in_32k();
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return imx_decode_pll(readl(&pll->spctl0), fref);
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}
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static ulong imx_decode_perclk(ulong div)
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{
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return lldiv((imx_get_mpllclk() * 2), (div * 3));
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}
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ulong imx_get_perclk1(void)
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{
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struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
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return imx_decode_perclk((readl(&pll->pcdr1) & 0x3f) + 1);
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}
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ulong imx_get_perclk2(void)
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{
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struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
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return imx_decode_perclk(((readl(&pll->pcdr1) >> 8) & 0x3f) + 1);
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}
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ulong imx_get_perclk3(void)
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{
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struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
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return imx_decode_perclk(((readl(&pll->pcdr1) >> 16) & 0x3f) + 1);
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}
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ulong imx_get_perclk4(void)
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{
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struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
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return imx_decode_perclk(((readl(&pll->pcdr1) >> 24) & 0x3f) + 1);
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}
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#if defined(CONFIG_DISPLAY_CPUINFO)
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int print_cpuinfo (void)
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{
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char buf[32];
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printf("CPU: Freescale i.MX27 at %s MHz\n\n",
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strmhz(buf, imx_get_mpllclk()));
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return 0;
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}
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#endif
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int cpu_eth_init(bd_t *bis)
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{
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#if defined(CONFIG_FEC_MXC)
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return fecmxc_initialize(bis);
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#else
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return 0;
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#endif
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}
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/*
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* Initializes on-chip MMC controllers.
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* to override, implement board_mmc_init()
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*/
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int cpu_mmc_init(bd_t *bis)
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{
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#ifdef CONFIG_MXC_MMC
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return mxc_mmc_init(bis);
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#else
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return 0;
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#endif
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}
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void imx_gpio_mode(int gpio_mode)
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{
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struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE;
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unsigned int pin = gpio_mode & GPIO_PIN_MASK;
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unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
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unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT;
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unsigned int aout = (gpio_mode & GPIO_AOUT_MASK) >> GPIO_AOUT_SHIFT;
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unsigned int bout = (gpio_mode & GPIO_BOUT_MASK) >> GPIO_BOUT_SHIFT;
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unsigned int tmp;
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/* Pullup enable */
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if (gpio_mode & GPIO_PUEN) {
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writel(readl(®s->port[port].puen) | (1 << pin),
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®s->port[port].puen);
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} else {
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writel(readl(®s->port[port].puen) & ~(1 << pin),
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®s->port[port].puen);
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}
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/* Data direction */
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if (gpio_mode & GPIO_OUT) {
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writel(readl(®s->port[port].ddir) | 1 << pin,
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®s->port[port].ddir);
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} else {
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writel(readl(®s->port[port].ddir) & ~(1 << pin),
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®s->port[port].ddir);
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}
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/* Primary / alternate function */
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if (gpio_mode & GPIO_AF) {
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writel(readl(®s->port[port].gpr) | (1 << pin),
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®s->port[port].gpr);
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} else {
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writel(readl(®s->port[port].gpr) & ~(1 << pin),
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®s->port[port].gpr);
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}
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/* use as gpio? */
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if (!(gpio_mode & (GPIO_PF | GPIO_AF))) {
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writel(readl(®s->port[port].gius) | (1 << pin),
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®s->port[port].gius);
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} else {
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writel(readl(®s->port[port].gius) & ~(1 << pin),
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®s->port[port].gius);
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}
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/* Output / input configuration */
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if (pin < 16) {
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tmp = readl(®s->port[port].ocr1);
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tmp &= ~(3 << (pin * 2));
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tmp |= (ocr << (pin * 2));
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writel(tmp, ®s->port[port].ocr1);
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writel(readl(®s->port[port].iconfa1) & ~(3 << (pin * 2)),
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®s->port[port].iconfa1);
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writel(readl(®s->port[port].iconfa1) | aout << (pin * 2),
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®s->port[port].iconfa1);
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writel(readl(®s->port[port].iconfb1) & ~(3 << (pin * 2)),
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®s->port[port].iconfb1);
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writel(readl(®s->port[port].iconfb1) | bout << (pin * 2),
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®s->port[port].iconfb1);
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} else {
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pin -= 16;
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tmp = readl(®s->port[port].ocr2);
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tmp &= ~(3 << (pin * 2));
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tmp |= (ocr << (pin * 2));
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writel(tmp, ®s->port[port].ocr2);
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writel(readl(®s->port[port].iconfa2) & ~(3 << (pin * 2)),
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®s->port[port].iconfa2);
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writel(readl(®s->port[port].iconfa2) | aout << (pin * 2),
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®s->port[port].iconfa2);
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writel(readl(®s->port[port].iconfb2) & ~(3 << (pin * 2)),
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®s->port[port].iconfb2);
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writel(readl(®s->port[port].iconfb2) | bout << (pin * 2),
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®s->port[port].iconfb2);
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}
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}
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#ifdef CONFIG_MXC_UART
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void mx27_uart_init_pins(void)
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{
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int i;
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unsigned int mode[] = {
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PE12_PF_UART1_TXD,
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PE13_PF_UART1_RXD,
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};
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for (i = 0; i < ARRAY_SIZE(mode); i++)
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imx_gpio_mode(mode[i]);
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}
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#endif /* CONFIG_MXC_UART */
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#ifdef CONFIG_FEC_MXC
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void mx27_fec_init_pins(void)
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{
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int i;
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unsigned int mode[] = {
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PD0_AIN_FEC_TXD0,
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PD1_AIN_FEC_TXD1,
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PD2_AIN_FEC_TXD2,
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PD3_AIN_FEC_TXD3,
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PD4_AOUT_FEC_RX_ER,
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PD5_AOUT_FEC_RXD1,
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PD6_AOUT_FEC_RXD2,
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PD7_AOUT_FEC_RXD3,
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PD8_AF_FEC_MDIO,
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PD9_AIN_FEC_MDC | GPIO_PUEN,
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PD10_AOUT_FEC_CRS,
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PD11_AOUT_FEC_TX_CLK,
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PD12_AOUT_FEC_RXD0,
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PD13_AOUT_FEC_RX_DV,
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PD14_AOUT_FEC_CLR,
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PD15_AOUT_FEC_COL,
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PD16_AIN_FEC_TX_ER,
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PF23_AIN_FEC_TX_EN,
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};
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for (i = 0; i < ARRAY_SIZE(mode); i++)
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imx_gpio_mode(mode[i]);
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}
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#endif /* CONFIG_FEC_MXC */
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#ifdef CONFIG_MXC_MMC
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void mx27_sd2_init_pins(void)
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{
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int i;
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unsigned int mode[] = {
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PB4_PF_SD2_D0,
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PB5_PF_SD2_D1,
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PB6_PF_SD2_D2,
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PB7_PF_SD2_D3,
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PB8_PF_SD2_CMD,
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PB9_PF_SD2_CLK,
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};
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for (i = 0; i < ARRAY_SIZE(mode); i++)
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imx_gpio_mode(mode[i]);
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}
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#endif /* CONFIG_MXC_MMC */
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