upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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274 lines
6.9 KiB
274 lines
6.9 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016, STMicroelectronics - All Rights Reserved
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* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <serial.h>
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#include <watchdog.h>
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#include <asm/io.h>
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#include <asm/arch/stm32.h>
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#include "serial_stm32.h"
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static void _stm32_serial_setbrg(fdt_addr_t base,
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struct stm32_uart_info *uart_info,
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u32 clock_rate,
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int baudrate)
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{
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bool stm32f4 = uart_info->stm32f4;
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u32 int_div, mantissa, fraction, oversampling;
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int_div = DIV_ROUND_CLOSEST(clock_rate, baudrate);
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if (int_div < 16) {
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oversampling = 8;
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setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
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} else {
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oversampling = 16;
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clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
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}
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mantissa = (int_div / oversampling) << USART_BRR_M_SHIFT;
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fraction = int_div % oversampling;
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writel(mantissa | fraction, base + BRR_OFFSET(stm32f4));
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}
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static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
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{
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struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
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_stm32_serial_setbrg(plat->base, plat->uart_info,
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plat->clock_rate, baudrate);
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return 0;
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}
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static int stm32_serial_setconfig(struct udevice *dev, uint serial_config)
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{
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struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
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bool stm32f4 = plat->uart_info->stm32f4;
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u8 uart_enable_bit = plat->uart_info->uart_enable_bit;
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u32 cr1 = plat->base + CR1_OFFSET(stm32f4);
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u32 config = 0;
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uint parity = SERIAL_GET_PARITY(serial_config);
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uint bits = SERIAL_GET_BITS(serial_config);
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uint stop = SERIAL_GET_STOP(serial_config);
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/*
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* only parity config is implemented, check if other serial settings
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* are the default one.
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* (STM32F4 serial IP didn't support parity setting)
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*/
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if (bits != SERIAL_8_BITS || stop != SERIAL_ONE_STOP || stm32f4)
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return -ENOTSUPP; /* not supported in driver*/
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clrbits_le32(cr1, USART_CR1_RE | USART_CR1_TE | BIT(uart_enable_bit));
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/* update usart configuration (uart need to be disable)
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* PCE: parity check enable
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* PS : '0' : Even / '1' : Odd
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* M[1:0] = '00' : 8 Data bits
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* M[1:0] = '01' : 9 Data bits with parity
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*/
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switch (parity) {
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default:
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case SERIAL_PAR_NONE:
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config = 0;
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break;
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case SERIAL_PAR_ODD:
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config = USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0;
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break;
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case SERIAL_PAR_EVEN:
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config = USART_CR1_PCE | USART_CR1_M0;
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break;
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}
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clrsetbits_le32(cr1,
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USART_CR1_PCE | USART_CR1_PS | USART_CR1_M1 |
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USART_CR1_M0,
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config);
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setbits_le32(cr1, USART_CR1_RE | USART_CR1_TE | BIT(uart_enable_bit));
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return 0;
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}
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static int stm32_serial_getc(struct udevice *dev)
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{
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struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
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bool stm32f4 = plat->uart_info->stm32f4;
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fdt_addr_t base = plat->base;
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u32 isr = readl(base + ISR_OFFSET(stm32f4));
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if ((isr & USART_ISR_RXNE) == 0)
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return -EAGAIN;
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if (isr & (USART_ISR_PE | USART_ISR_ORE)) {
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if (!stm32f4)
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setbits_le32(base + ICR_OFFSET,
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USART_ICR_PCECF | USART_ICR_ORECF);
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else
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readl(base + RDR_OFFSET(stm32f4));
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return -EIO;
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}
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return readl(base + RDR_OFFSET(stm32f4));
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}
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static int _stm32_serial_putc(fdt_addr_t base,
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struct stm32_uart_info *uart_info,
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const char c)
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{
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bool stm32f4 = uart_info->stm32f4;
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if ((readl(base + ISR_OFFSET(stm32f4)) & USART_ISR_TXE) == 0)
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return -EAGAIN;
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writel(c, base + TDR_OFFSET(stm32f4));
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return 0;
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}
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static int stm32_serial_putc(struct udevice *dev, const char c)
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{
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struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
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return _stm32_serial_putc(plat->base, plat->uart_info, c);
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}
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static int stm32_serial_pending(struct udevice *dev, bool input)
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{
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struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
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bool stm32f4 = plat->uart_info->stm32f4;
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fdt_addr_t base = plat->base;
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if (input)
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return readl(base + ISR_OFFSET(stm32f4)) &
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USART_ISR_RXNE ? 1 : 0;
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else
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return readl(base + ISR_OFFSET(stm32f4)) &
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USART_ISR_TXE ? 0 : 1;
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}
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static void _stm32_serial_init(fdt_addr_t base,
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struct stm32_uart_info *uart_info)
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{
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bool stm32f4 = uart_info->stm32f4;
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u8 uart_enable_bit = uart_info->uart_enable_bit;
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/* Disable uart-> enable fifo -> enable uart */
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clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
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BIT(uart_enable_bit));
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if (uart_info->has_fifo)
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setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_FIFOEN);
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setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
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BIT(uart_enable_bit));
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}
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static int stm32_serial_probe(struct udevice *dev)
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{
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struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
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struct clk clk;
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int ret;
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plat->uart_info = (struct stm32_uart_info *)dev_get_driver_data(dev);
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret < 0)
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return ret;
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ret = clk_enable(&clk);
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if (ret) {
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dev_err(dev, "failed to enable clock\n");
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return ret;
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}
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plat->clock_rate = clk_get_rate(&clk);
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if (plat->clock_rate < 0) {
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clk_disable(&clk);
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return plat->clock_rate;
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};
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_stm32_serial_init(plat->base, plat->uart_info);
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return 0;
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}
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static const struct udevice_id stm32_serial_id[] = {
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{ .compatible = "st,stm32-uart", .data = (ulong)&stm32f4_info},
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{ .compatible = "st,stm32f7-uart", .data = (ulong)&stm32f7_info},
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{ .compatible = "st,stm32h7-uart", .data = (ulong)&stm32h7_info},
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{}
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};
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static int stm32_serial_ofdata_to_platdata(struct udevice *dev)
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{
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struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
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plat->base = devfdt_get_addr(dev);
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if (plat->base == FDT_ADDR_T_NONE)
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return -EINVAL;
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return 0;
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}
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static const struct dm_serial_ops stm32_serial_ops = {
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.putc = stm32_serial_putc,
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.pending = stm32_serial_pending,
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.getc = stm32_serial_getc,
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.setbrg = stm32_serial_setbrg,
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.setconfig = stm32_serial_setconfig
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};
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U_BOOT_DRIVER(serial_stm32) = {
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.name = "serial_stm32",
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.id = UCLASS_SERIAL,
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.of_match = of_match_ptr(stm32_serial_id),
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.ofdata_to_platdata = of_match_ptr(stm32_serial_ofdata_to_platdata),
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.platdata_auto_alloc_size = sizeof(struct stm32x7_serial_platdata),
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.ops = &stm32_serial_ops,
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.probe = stm32_serial_probe,
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.flags = DM_FLAG_PRE_RELOC,
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};
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#ifdef CONFIG_DEBUG_UART_STM32
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#include <debug_uart.h>
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static inline struct stm32_uart_info *_debug_uart_info(void)
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{
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struct stm32_uart_info *uart_info;
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#if defined(CONFIG_STM32F4)
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uart_info = &stm32f4_info;
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#elif defined(CONFIG_STM32F7)
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uart_info = &stm32f7_info;
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#else
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uart_info = &stm32h7_info;
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#endif
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return uart_info;
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}
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static inline void _debug_uart_init(void)
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{
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fdt_addr_t base = CONFIG_DEBUG_UART_BASE;
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struct stm32_uart_info *uart_info = _debug_uart_info();
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_stm32_serial_init(base, uart_info);
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_stm32_serial_setbrg(base, uart_info,
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CONFIG_DEBUG_UART_CLOCK,
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CONFIG_BAUDRATE);
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printf("DEBUG done\n");
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}
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static inline void _debug_uart_putc(int c)
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{
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fdt_addr_t base = CONFIG_DEBUG_UART_BASE;
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struct stm32_uart_info *uart_info = _debug_uart_info();
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while (_stm32_serial_putc(base, uart_info, c) == -EAGAIN)
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WATCHDOG_RESET();
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}
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DEBUG_UART_FUNCS
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#endif
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