upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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136 lines
3.4 KiB
136 lines
3.4 KiB
/*
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* Andestech ATFSDC010 SD/MMC driver
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*
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* (C) Copyright 2017
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* Rick Chen, NDS32 Software Engineering, rick@andestech.com
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <dt-structs.h>
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#include <errno.h>
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#include <mapmem.h>
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#include <mmc.h>
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#include <pwrseq.h>
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#include <syscon.h>
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#include <linux/err.h>
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#include <faraday/ftsdc010.h>
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#include "ftsdc010_mci.h"
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DECLARE_GLOBAL_DATA_PTR;
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct nds_mmc {
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fdt32_t bus_width;
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bool cap_mmc_highspeed;
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bool cap_sd_highspeed;
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fdt32_t clock_freq_min_max[2];
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struct phandle_2_cell clocks[4];
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fdt32_t fifo_depth;
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fdt32_t reg[2];
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};
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#endif
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struct nds_mmc_plat {
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct nds_mmc dtplat;
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#endif
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struct mmc_config cfg;
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struct mmc mmc;
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};
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struct ftsdc_priv {
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struct clk clk;
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struct ftsdc010_chip chip;
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int fifo_depth;
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bool fifo_mode;
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u32 minmax[2];
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};
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static int nds32_mmc_ofdata_to_platdata(struct udevice *dev)
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{
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#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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struct ftsdc_priv *priv = dev_get_priv(dev);
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struct ftsdc010_chip *chip = &priv->chip;
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chip->name = dev->name;
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chip->ioaddr = (void *)devfdt_get_addr(dev);
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chip->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
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"bus-width", 4);
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chip->priv = dev;
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priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
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"fifo-depth", 0);
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priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
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"fifo-mode");
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if (fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
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"clock-freq-min-max", priv->minmax, 2)) {
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int val = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
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"max-frequency", -EINVAL);
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if (val < 0)
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return val;
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priv->minmax[0] = 400000; /* 400 kHz */
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priv->minmax[1] = val;
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} else {
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debug("%s: 'clock-freq-min-max' property was deprecated.\n",
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__func__);
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}
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#endif
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chip->sclk = priv->minmax[1];
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chip->regs = chip->ioaddr;
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return 0;
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}
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static int nds32_mmc_probe(struct udevice *dev)
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{
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struct nds_mmc_plat *plat = dev_get_platdata(dev);
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struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
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struct ftsdc_priv *priv = dev_get_priv(dev);
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struct ftsdc010_chip *chip = &priv->chip;
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struct udevice *pwr_dev __maybe_unused;
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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int ret;
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struct nds_mmc *dtplat = &plat->dtplat;
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chip->name = dev->name;
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chip->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
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chip->buswidth = dtplat->bus_width;
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chip->priv = dev;
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chip->dev_index = 1;
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memcpy(priv->minmax, dtplat->clock_freq_min_max, sizeof(priv->minmax));
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ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
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if (ret < 0)
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return ret;
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#endif
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ftsdc_setup_cfg(&plat->cfg, dev->name, chip->buswidth, chip->caps,
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priv->minmax[1] , priv->minmax[0]);
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chip->mmc = &plat->mmc;
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chip->mmc->priv = &priv->chip;
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chip->mmc->dev = dev;
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upriv->mmc = chip->mmc;
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return ftsdc010_probe(dev);
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}
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static int nds32_mmc_bind(struct udevice *dev)
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{
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struct nds_mmc_plat *plat = dev_get_platdata(dev);
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return ftsdc010_bind(dev, &plat->mmc, &plat->cfg);
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}
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static const struct udevice_id nds32_mmc_ids[] = {
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{ .compatible = "andestech,atsdc010" },
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{ }
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};
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U_BOOT_DRIVER(nds32_mmc_drv) = {
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.name = "nds32_mmc",
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.id = UCLASS_MMC,
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.of_match = nds32_mmc_ids,
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.ofdata_to_platdata = nds32_mmc_ofdata_to_platdata,
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.ops = &dm_ftsdc010_ops,
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.bind = nds32_mmc_bind,
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.probe = nds32_mmc_probe,
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.priv_auto_alloc_size = sizeof(struct ftsdc_priv),
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.platdata_auto_alloc_size = sizeof(struct nds_mmc_plat),
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};
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