upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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88 lines
2.3 KiB
88 lines
2.3 KiB
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <fsl_ddr_sdram.h>
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#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
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#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
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#endif
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void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
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unsigned int ctrl_num, int step)
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{
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unsigned int i;
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struct ccsr_ddr __iomem *ddr =
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(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
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if (ctrl_num != 0) {
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printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
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return;
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}
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for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
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if (i == 0) {
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out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
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out_be32(&ddr->cs0_config, regs->cs[i].config);
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} else if (i == 1) {
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out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
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out_be32(&ddr->cs1_config, regs->cs[i].config);
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} else if (i == 2) {
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out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
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out_be32(&ddr->cs2_config, regs->cs[i].config);
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} else if (i == 3) {
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out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
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out_be32(&ddr->cs3_config, regs->cs[i].config);
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}
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}
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out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
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out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
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out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
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out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
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#if defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_ARCH_MPC8541)
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out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
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#endif
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/*
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* 200 painful micro-seconds must elapse between
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* the DDR clock setup and the DDR config enable.
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*/
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udelay(200);
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asm volatile("sync;isync");
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out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
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asm("sync;isync;msync");
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udelay(500);
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}
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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/*
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* Initialize all of memory for ECC, then enable errors.
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*/
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void
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ddr_enable_ecc(unsigned int dram_size)
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{
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struct ccsr_ddr __iomem *ddr =
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(struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
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dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);
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/*
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* Enable errors for ECC.
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*/
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debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
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ddr->err_disable = 0x00000000;
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asm("sync;isync;msync");
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debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
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}
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#endif /* CONFIG_DDR_ECC && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */
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