upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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474 lines
15 KiB
474 lines
15 KiB
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Based on corenet_ds.h
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_ARCH_P5040)
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#error Must call Cyrus CONFIG with a specific CPU enabled.
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#endif
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#define CONFIG_SDCARD
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#define CONFIG_FSL_SATA_V2
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#define CONFIG_PCIE3
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#define CONFIG_PCIE4
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#ifdef CONFIG_ARCH_P5020
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#define CONFIG_SYS_FSL_RAID_ENGINE
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#define CONFIG_SYS_DPAA_RMAN
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#endif
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#define CONFIG_SYS_DPAA_PME
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/*
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* Corenet DS style board configuration file
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*/
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#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
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#define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg
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#if defined(CONFIG_ARCH_P5020)
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#define CONFIG_SYS_CLK_FREQ 133000000
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#define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg
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#elif defined(CONFIG_ARCH_P5040)
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#define CONFIG_SYS_CLK_FREQ 100000000
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#define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg
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#endif
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/* High Level Configuration Options */
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#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
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#define CONFIG_SYS_MMC_MAX_DEVICE 1
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#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
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#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
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#define CONFIG_PCIE1 /* PCIE controller 1 */
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#define CONFIG_PCIE2 /* PCIE controller 2 */
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#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
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#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
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#define CONFIG_ENV_OVERWRITE
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#if defined(CONFIG_SDCARD)
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#define CONFIG_SYS_EXTRA_ENV_RELOC
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#define CONFIG_FSL_FIXED_MMC_LOCATION
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_OFFSET (512 * 1658)
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#endif
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/*
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* These can be toggled for performance analysis, otherwise use default.
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*/
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#define CONFIG_SYS_CACHE_STASHING
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#define CONFIG_BACKSIDE_L2_CACHE
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#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
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#define CONFIG_BTB /* toggle branch predition */
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#define CONFIG_DDR_ECC
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#ifdef CONFIG_DDR_ECC
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#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
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#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
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#endif
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#define CONFIG_ENABLE_36BIT_PHYS
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_ADDR_MAP
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#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
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#endif
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/* test POST memory test */
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#undef CONFIG_POST
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#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x00400000
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/*
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* Config the L3 Cache as L3 SRAM
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*/
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#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
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#else
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#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
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#endif
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#define CONFIG_SYS_L3_SIZE (1024 << 10)
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#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_DCSRBAR 0xf0000000
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#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
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#endif
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/*
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* DDR Setup
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*/
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#define CONFIG_VERY_BIG_RAM
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_DIMM_SLOTS_PER_CTLR 1
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#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
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#define CONFIG_DDR_SPD
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#define CONFIG_SYS_SPD_BUS_NUM 1
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#define SPD_EEPROM_ADDRESS1 0x51
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#define SPD_EEPROM_ADDRESS2 0x52
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#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
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/*
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* Local Bus Definitions
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*/
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#define CONFIG_SYS_LBC0_BASE 0xe0000000 /* Start of LBC Registers */
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_LBC0_BASE_PHYS 0xfe0000000ull
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#else
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#define CONFIG_SYS_LBC0_BASE_PHYS CONFIG_SYS_LBC0_BASE
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#endif
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#define CONFIG_SYS_LBC1_BASE 0xe1000000 /* Start of LBC Registers */
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_LBC1_BASE_PHYS 0xfe1000000ull
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#else
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#define CONFIG_SYS_LBC1_BASE_PHYS CONFIG_SYS_LBC1_BASE
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#endif
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/* Set the local bus clock 1/16 of platform clock */
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#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_16 | LCRR_EADC_1)
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#define CONFIG_SYS_BR0_PRELIM \
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(BR_PHYS_ADDR(CONFIG_SYS_LBC0_BASE_PHYS) | BR_PS_16 | BR_V)
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#define CONFIG_SYS_BR1_PRELIM \
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(BR_PHYS_ADDR(CONFIG_SYS_LBC1_BASE_PHYS) | BR_PS_16 | BR_V)
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#define CONFIG_SYS_OR0_PRELIM 0xfff00010
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#define CONFIG_SYS_OR1_PRELIM 0xfff00010
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#if defined(CONFIG_RAMBOOT_PBL)
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#define CONFIG_SYS_RAMBOOT
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#endif
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#define CONFIG_HWCONFIG
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/* define to use L1 as initial stack */
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#define CONFIG_L1_INIT_RAM
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#define CONFIG_SYS_INIT_RAM_LOCK
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#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
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/* The assembler doesn't like typecast */
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
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((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
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CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
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#else
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
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#endif
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#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
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/* Serial Port - controlled on board with jumper J8
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* open - index 2
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* shorted - index 1
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*/
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
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#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
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#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_I2C_MULTI_BUS
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#define CONFIG_I2C_CMD_TREE
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#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
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#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed and slave address */
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#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
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#define CONFIG_SYS_FSL_I2C3_SPEED 400000 /* I2C speed and slave address */
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#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
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#define CONFIG_SYS_FSL_I2C4_SPEED 400000 /* I2C speed and slave address */
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#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
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#define CONFIG_ID_EEPROM
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#define CONFIG_SYS_I2C_EEPROM_NXID
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#define CONFIG_SYS_EEPROM_BUS_NUM 0
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
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#define CONFIG_SYS_I2C_GENERIC_MAC
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#define CONFIG_SYS_I2C_MAC1_BUS 3
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#define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57
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#define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2
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#define CONFIG_SYS_I2C_MAC2_BUS 0
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#define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50
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#define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa
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#define CONFIG_RTC_MCP79411 1
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#define CONFIG_SYS_RTC_BUS_NUM 3
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#define CONFIG_SYS_I2C_RTC_ADDR 0x6f
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/*
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* eSPI - Enhanced SPI
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*/
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/*
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* General PCI
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* Memory space is mapped 1-1, but I/O space must start from 0.
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*/
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/* controller 1, direct to uli, tgtid 3, Base address 20000 */
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#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
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#else
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#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
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#endif
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#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
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#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
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#else
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
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#endif
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#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
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/* controller 2, Slot 2, tgtid 2, Base address 201000 */
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#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
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#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
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#else
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#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
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#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
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#endif
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#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
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#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
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#else
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#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
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#endif
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#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
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/* controller 3, Slot 1, tgtid 1, Base address 202000 */
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#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
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#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
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#else
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#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
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#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
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#endif
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#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
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#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
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#else
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#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
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#endif
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#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
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/* controller 4, Base address 203000 */
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#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
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#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
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#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
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#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
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#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
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/* Qman/Bman */
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#define CONFIG_SYS_BMAN_NUM_PORTALS 10
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#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
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#else
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#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
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#endif
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#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
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#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
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#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
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#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
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#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
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#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
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CONFIG_SYS_BMAN_CENA_SIZE)
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#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
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#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
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#define CONFIG_SYS_QMAN_NUM_PORTALS 10
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#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
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#else
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#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
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#endif
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#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
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#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
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#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
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#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
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#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
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#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
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CONFIG_SYS_QMAN_CENA_SIZE)
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#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
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#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
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#define CONFIG_SYS_DPAA_FMAN
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/* Default address of microcode for the Linux Fman driver */
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/*
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* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
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* about 825KB (1650 blocks), Env is stored after the image, and the env size is
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* 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
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*/
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#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
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#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
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#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
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#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
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#ifdef CONFIG_SYS_DPAA_FMAN
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#define CONFIG_FMAN_ENET
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#endif
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#ifdef CONFIG_PCI
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#define CONFIG_PCI_INDIRECT_BRIDGE
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#endif /* CONFIG_PCI */
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/* SATA */
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#ifdef CONFIG_FSL_SATA_V2
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#define CONFIG_SYS_SATA_MAX_DEVICE 2
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#define CONFIG_SATA1
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#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
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#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
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#define CONFIG_SATA2
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#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
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#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
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#define CONFIG_LBA48
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#endif
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#ifdef CONFIG_FMAN_ENET
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#define CONFIG_SYS_TBIPA_VALUE 8
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#define CONFIG_ETHPRIME "FM1@DTSEC4"
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#endif
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/*
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* Environment
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*/
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#define CONFIG_LOADS_ECHO /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
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/*
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* USB
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*/
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#define CONFIG_HAS_FSL_DR_USB
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#define CONFIG_HAS_FSL_MPH_USB
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#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
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#define CONFIG_USB_EHCI_FSL
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
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#define CONFIG_EHCI_IS_TDI
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/* _VIA_CONTROL_EP */
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#endif
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#ifdef CONFIG_MMC
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#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
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#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
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#endif
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 64 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
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#ifdef CONFIG_CMD_KGDB
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#endif
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/*
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* Environment Configuration
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*/
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#define CONFIG_ROOTPATH "/opt/nfsroot"
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#define CONFIG_BOOTFILE "uImage"
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#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
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/* default location for tftp and bootm */
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#define CONFIG_LOADADDR 1000000
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#define __USB_PHY_TYPE utmi
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
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"bank_intlv=cs0_cs1;" \
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"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
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"usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
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"netdev=eth0\0" \
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"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
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"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
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"consoledev=ttyS0\0" \
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"ramdiskaddr=2000000\0" \
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"fdtaddr=1e00000\0" \
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"bdev=sda3\0"
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#define CONFIG_HDBOOT \
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"setenv bootargs root=/dev/$bdev rw " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr - $fdtaddr"
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#define CONFIG_NFSBOOTCOMMAND \
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"setenv bootargs root=/dev/nfs rw " \
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"nfsroot=$serverip:$rootpath " \
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"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr - $fdtaddr"
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#define CONFIG_RAMBOOTCOMMAND \
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"setenv bootargs root=/dev/ram rw " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $ramdiskaddr $ramdiskfile;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr $ramdiskaddr $fdtaddr"
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#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
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#include <asm/fsl_secure_boot.h>
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#endif /* __CONFIG_H */
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