upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
599 lines
17 KiB
599 lines
17 KiB
/*
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* Copyright (C) 2007 Freescale Semiconductor, Inc.
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*
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* Copyright (C) 2011 Matrix Vision GmbH
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* Andre Schwarz <andre.schwarz@matrix-vision.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <version.h>
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_E300 1
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#define CONFIG_MPC837x 1
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#define CONFIG_MPC8377 1
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#define CONFIG_SYS_TEXT_BASE 0xFC000000
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#define CONFIG_PCI 1
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#define CONFIG_PCI_INDIRECT_BRIDGE 1
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#define CONFIG_MASK_AER_AO
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#define CONFIG_DISPLAY_AER_FULL
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#define CONFIG_MISC_INIT_R
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/*
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* On-board devices
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*/
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#define CONFIG_TSEC_ENET
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/*
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* System Clock Setup
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*/
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#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
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#define CONFIG_PCIE
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#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
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#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
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/*
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* Hardware Reset Configuration Word stored in EEPROM.
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*/
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#define CONFIG_SYS_HRCW_LOW 0
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#define CONFIG_SYS_HRCW_HIGH 0
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/* Arbiter Configuration Register */
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#define CONFIG_SYS_ACR_PIPE_DEP 3
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#define CONFIG_SYS_ACR_RPTCNT 3
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/* System Priority Control Regsiter */
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#define CONFIG_SYS_SPCR_TSECEP 3
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/* System Clock Configuration Register */
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#define CONFIG_SYS_SCCR_TSEC1CM 3
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#define CONFIG_SYS_SCCR_TSEC2CM 0
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#define CONFIG_SYS_SCCR_SDHCCM 3
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#define CONFIG_SYS_SCCR_ENCCM 3 /* also clock for I2C-1 */
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#define CONFIG_SYS_SCCR_USBDRCM CONFIG_SYS_SCCR_ENCCM /* must match */
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#define CONFIG_SYS_SCCR_PCIEXP1CM 3
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#define CONFIG_SYS_SCCR_PCIEXP2CM 3
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#define CONFIG_SYS_SCCR_PCICM 1
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#define CONFIG_SYS_SCCR_SATACM 0xFF
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/*
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* System IO Config
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*/
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#define CONFIG_SYS_SICRH 0x087c0000
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#define CONFIG_SYS_SICRL 0x40000000
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/*
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* Output Buffer Impedance
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*/
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#define CONFIG_SYS_OBIR 0x30000000
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/*
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* IMMR new address
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*/
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#define CONFIG_SYS_IMMR 0xE0000000
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/*
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* DDR Setup
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*/
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#define CONFIG_SYS_DDR_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_SYS_83XX_DDR_USES_CS0
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#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN | DDRCDR_PZ_HIZ |\
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DDRCDR_NZ_HIZ | DDRCDR_ODT |\
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DDRCDR_Q_DRN)
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#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
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#define CONFIG_SYS_DDR_MODE_WEAK
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#define CONFIG_SYS_DDR_WRITE_DATA_DELAY 2
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#define CONFIG_SYS_DDR_CPO 0x1f
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/* SPD table located at offset 0x20 in extended adressing ROM
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* used for HRCW fetch after power-on reset
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*/
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#define CONFIG_SPD_EEPROM
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#define SPD_EEPROM_ADDRESS 0x50
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#define SPD_EEPROM_OFFSET 0x20
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#define SPD_EEPROM_ADDR_LEN 2
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/*
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* The reserved memory
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*/
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_MONITOR_LEN (512*1024)
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#define CONFIG_SYS_MALLOC_LEN (512*1024)
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/*
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* Initial RAM Base Address Setup
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*/
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#define CONFIG_SYS_INIT_RAM_LOCK 1
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#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE -\
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GENERATED_GBL_DATA_SIZE)
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/*
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* Local Bus Configuration & Clock Setup
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*/
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#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
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#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
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#define CONFIG_SYS_LBC_LBCR 0x00000000
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#define CONFIG_FSL_ELBC 1
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/*
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* FLASH on the Local Bus
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*/
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
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#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_FLASH_SIZE 64
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#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
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#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 |\
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BR_MS_GPCM | BR_V)
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#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_FLASH_BASE | OR_UPM_XAM |\
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OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 |\
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OR_GPCM_XACS | OR_GPCM_SCY_15 |\
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OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET |\
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OR_GPCM_EAD)
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 512
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#undef CONFIG_SYS_FLASH_CHECKSUM
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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/*
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* NAND Flash on the Local Bus
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*/
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#define CONFIG_MTD_NAND_VERIFY_WRITE 1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_NAND_FSL_ELBC 1
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#define CONFIG_SYS_NAND_BASE 0xE0600000
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#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE | BR_DECC_CHK_GEN |\
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BR_PS_8 | BR_MS_FCM | BR_V)
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#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_BCTLD | OR_FCM_CST |\
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OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_RST |\
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OR_FCM_TRLX | OR_FCM_EHTR)
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#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
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#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
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/*
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* Serial Port
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*/
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
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#define CONFIG_CONSOLE ttyS0
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#define CONFIG_BAUDRATE 115200
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/* SERDES */
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#define CONFIG_FSL_SERDES
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#define CONFIG_FSL_SERDES1 0xe3000
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#define CONFIG_FSL_SERDES2 0xe3100
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/* Use the HUSH parser */
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#define CONFIG_SYS_HUSH_PARSER
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/* Pass open firmware flat tree */
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_OF_BOARD_SETUP 1
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#define CONFIG_OF_STDOUT_VIA_ALIAS 1
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
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#define CONFIG_SYS_FSL_I2C2_SPEED 400000
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#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
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/*
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* General PCI
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* Addresses are mapped 1-1.
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*/
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#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
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#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
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#define CONFIG_SYS_PCI_MEM_SIZE (256 << 20)
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#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
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#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
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#define CONFIG_SYS_PCI_MMIO_SIZE (256 << 20)
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#define CONFIG_SYS_PCI_IO_BASE 0x00000000
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#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
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#define CONFIG_SYS_PCI_IO_SIZE (1 << 20)
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#ifdef CONFIG_PCIE
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#define CONFIG_SYS_PCIE1_BASE 0xA0000000
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#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
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#define CONFIG_SYS_PCIE1_CFG_SIZE (128 << 20)
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#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
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#define CONFIG_SYS_PCIE1_MEM_SIZE (256 << 20)
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#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
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#define CONFIG_SYS_PCIE1_IO_SIZE (8 << 20)
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#define CONFIG_SYS_PCIE2_BASE 0xC0000000
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#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
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#define CONFIG_SYS_PCIE2_CFG_SIZE (128 << 20)
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#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
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#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
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#define CONFIG_SYS_PCIE2_MEM_SIZE (256 << 20)
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#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
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#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
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#define CONFIG_SYS_PCIE2_IO_SIZE (8 << 20)
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#endif
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#define CONFIG_PCI_PNP
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#define CONFIG_PCI_SCAN_SHOW
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#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
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/*
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* TSEC
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*/
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#define CONFIG_GMII /* MII PHY management */
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#define CONFIG_SYS_VSC8601_SKEWFIX
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#define CONFIG_SYS_VSC8601_SKEW_TX 3
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#define CONFIG_SYS_VSC8601_SKEW_RX 3
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#define CONFIG_TSEC1
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#define CONFIG_HAS_ETH0
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#define CONFIG_TSEC1_NAME "TSEC0"
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#define CONFIG_SYS_TSEC1_OFFSET 0x24000
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#define TSEC1_PHY_ADDR 0x10
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#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC1_PHYIDX 0
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#define CONFIG_ETHPRIME "TSEC0"
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#define CONFIG_HAS_ETH0
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/*
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* SATA
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*/
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#define CONFIG_LIBATA
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#define CONFIG_FSL_SATA
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#define CONFIG_SYS_SATA_MAX_DEVICE 2
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#define CONFIG_SATA1
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#define CONFIG_SYS_SATA1_OFFSET 0x18000
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#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
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#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
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#define CONFIG_SATA2
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#define CONFIG_SYS_SATA2_OFFSET 0x19000
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#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
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#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
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#define CONFIG_LBA48
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#define CONFIG_CMD_SATA
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#define CONFIG_DOS_PARTITION
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#define CONFIG_CMD_EXT2
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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#define CONFIG_BOOTP_VENDOREX
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_BOOTP_DNS
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#define CONFIG_BOOTP_DNS2
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#define CONFIG_BOOTP_NTPSERVER
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#define CONFIG_BOOTP_RANDOM_DELAY
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#define CONFIG_BOOTP_SEND_HOSTNAME
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#define CONFIG_LIB_RAND
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_USB
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#define CONFIG_CMD_SPI
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_UBI
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#define CONFIG_CMD_UBIFS
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#define CONFIG_CMD_MTDPARTS
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#define CONFIG_CMD_SATA
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_JFFS2
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#define CONFIG_RBTREE
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#define CONFIG_LZO
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#define CONFIG_MTD_DEVICE
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#define CONFIG_MTD_PARTITIONS
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#define CONFIG_FLASH_CFI_MTD
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#define MTDIDS_DEFAULT "nor0=NOR,nand0=NAND"
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#define MTDPARTS_DEFAULT "mtdparts=NOR:1M(u-boot),2M(FPGA);NAND:-(root)"
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#define CONFIG_FIT
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#define CONFIG_FIT_VERBOSE 1
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#define CONFIG_CMDLINE_EDITING 1
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#define CONFIG_AUTO_COMPLETE
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_SYS_LOAD_ADDR 0x2000000
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#define CONFIG_LOADADDR 0x4000000
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#define CONFIG_SYS_CBSIZE 256
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_LOADS_ECHO 1
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
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#define CONFIG_SYS_MEMTEST_START (60<<20)
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#define CONFIG_SYS_MEMTEST_END (70<<20)
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 256 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
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/*
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* Core HID Setup
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*/
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#define CONFIG_SYS_HID0_INIT 0x000000000
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#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
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HID0_ENABLE_INSTRUCTION_CACHE)
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#define CONFIG_SYS_HID2 HID2_HBE
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/*
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* MMU Setup
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*/
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#define CONFIG_HIGH_BATS 1
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/* DDR: cache cacheable */
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#define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM | BATL_PP_RW |\
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BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM | BATU_BL_256M | BATU_VS |\
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BATU_VP)
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#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
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#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
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/* unused */
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#define CONFIG_SYS_IBAT1L (0)
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#define CONFIG_SYS_IBAT1U (0)
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#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
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#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
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/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
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#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR | BATL_PP_RW |\
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS |\
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BATU_VP)
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#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
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#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
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/* unused */
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#define CONFIG_SYS_IBAT3L (0)
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#define CONFIG_SYS_IBAT3U (0)
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#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
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#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
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/* FLASH: icache cacheable, but dcache-inhibit and guarded */
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#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW |\
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BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE | BATU_BL_64M |\
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BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
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/* Stack in dcache: cacheable, no memory coherence */
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#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
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#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K |\
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BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
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#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
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/* PCI MEM space: cacheable */
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#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_RW |\
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BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M |\
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BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
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#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
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/* PCI MMIO space: cache-inhibit and guarded */
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#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_RW | \
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M |\
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BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
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#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
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|
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/*
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* I2C EEPROM settings
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*/
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
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#define CONFIG_SYS_EEPROM_SIZE 0x4000
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|
|
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/*
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* Environment Configuration
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|
*/
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|
#define CONFIG_SYS_FLASH_PROTECTION
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_ENV_IS_IN_FLASH 1
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|
#define CONFIG_ENV_ADDR 0xFFD00000
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|
#define CONFIG_ENV_SECT_SIZE 0x20000
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#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
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|
|
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/*
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|
* Video
|
|
*/
|
|
#define CONFIG_VIDEO
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|
#define CONFIG_VIDEO_SM501_PCI
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|
#define VIDEO_FB_LITTLE_ENDIAN
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|
#define CONFIG_CMD_BMP
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|
#define CONFIG_VIDEO_SM501
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|
#define CONFIG_VIDEO_SM501_32BPP
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|
#define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000
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|
#define CONFIG_CFB_CONSOLE
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|
#define CONFIG_VIDEO_LOGO
|
|
#define CONFIG_VIDEO_BMP_LOGO
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|
#define CONFIG_VGA_AS_SINGLE_DEVICE
|
|
#define CONFIG_SPLASH_SCREEN
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|
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
|
|
#define CONFIG_VIDEO_BMP_GZIP
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|
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
|
|
|
|
/*
|
|
* SPI
|
|
*/
|
|
#define CONFIG_MPC8XXX_SPI
|
|
|
|
/*
|
|
* USB
|
|
*/
|
|
#define CONFIG_SYS_USB_HOST
|
|
#define CONFIG_USB_EHCI
|
|
#define CONFIG_USB_EHCI_FSL
|
|
#define CONFIG_HAS_FSL_DR_USB
|
|
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
|
|
|
#define CONFIG_USB_STORAGE
|
|
#define CONFIG_USB_KEYBOARD
|
|
/*
|
|
*
|
|
*/
|
|
#define CONFIG_BOOTDELAY 5
|
|
#define CONFIG_AUTOBOOT_KEYED
|
|
#define CONFIG_AUTOBOOT_STOP_STR "s"
|
|
#define CONFIG_ZERO_BOOTDELAY_CHECK
|
|
#define CONFIG_RESET_TO_RETRY 1000
|
|
|
|
#define MV_CI "MergerBox"
|
|
#define MV_VCI "MergerBox"
|
|
#define MV_FPGA_DATA 0xfc100000
|
|
#define MV_FPGA_SIZE 0x00200000
|
|
|
|
#define CONFIG_SHOW_BOOT_PROGRESS 1
|
|
|
|
#define MV_KERNEL_ADDR_RAM 0x02800000
|
|
#define MV_DTB_ADDR_RAM 0x00600000
|
|
#define MV_INITRD_ADDR_RAM 0x01000000
|
|
#define MV_FITADDR 0xfc300000
|
|
#define MV_SPLAH_ADDR 0xffe00000
|
|
|
|
#define CONFIG_BOOTCOMMAND "run i2c_init;if test ${boot_sqfs} -eq 1;"\
|
|
"then; run fitboot;else;run ubiboot;fi;"
|
|
#define CONFIG_BOOTARGS "console=ttyS0,115200n8"
|
|
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
"console_nr=0\0"\
|
|
"stdin=serial\0"\
|
|
"stdout=serial\0"\
|
|
"stderr=serial\0"\
|
|
"boot_sqfs=1\0"\
|
|
"usb_dr_mode=host\0"\
|
|
"bootfile=MergerBox.fit\0"\
|
|
"baudrate=" __stringify(CONFIG_BAUDRATE) "\0"\
|
|
"fpga=0\0"\
|
|
"fpgadata=" __stringify(MV_FPGA_DATA) "\0"\
|
|
"fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0"\
|
|
"mv_kernel_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0"\
|
|
"mv_initrd_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0"\
|
|
"mv_dtb_ram=" __stringify(MV_DTB_ADDR_RAM) "\0"\
|
|
"uboota=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"\
|
|
"fitaddr=" __stringify(MV_FITADDR) "\0"\
|
|
"mv_version=" U_BOOT_VERSION "\0"\
|
|
"mtdids=" MTDIDS_DEFAULT "\0"\
|
|
"mtdparts=" MTDPARTS_DEFAULT "\0"\
|
|
"dhcp_client_id=" MV_CI "\0"\
|
|
"dhcp_vendor-class-identifier=" MV_VCI "\0"\
|
|
"upd_uboot=dhcp;tftp bdi2000/u-boot-mergerbox-xp.bin;"\
|
|
"protect off all;erase $uboota +0xC0000;"\
|
|
"cp.b $loadaddr $uboota $filesize\0"\
|
|
"upd_fpga=dhcp;tftp MergerBox.rbf;erase $fpgadata +$fpgadatasize;"\
|
|
"cp.b $loadaddr $fpgadata $filesize\0"\
|
|
"upd_fit=dhcp;tftp MergerBox.fit;erase $fitaddr +0x1000000;"\
|
|
"cp.b $loadaddr $fitaddr $filesize\0"\
|
|
"addsqshrfs=set bootargs $bootargs root=/dev/ram ro "\
|
|
"rootfstype=squashfs\0"\
|
|
"addubirfs=set bootargs $bootargs ubi.mtd=9 root=ubi0:rootfs rw "\
|
|
"rootfstype=ubifs\0"\
|
|
"addusbrfs=set bootargs $bootargs root=/dev/sda1 rw "\
|
|
"rootfstype=ext3 usb-storage.delay_use=1 rootdelay=3\0"\
|
|
"netusbboot=bootp;run fpganetload fitnetload addusbrfs doboot\0"\
|
|
"netubiboot= bootp;run fpganetload fitnetload addubirfs doboot\0"\
|
|
"ubiboot=run fitprep addubirfs;set mv_initrd_ram -;run doboot\0"\
|
|
"doboot=bootm $mv_kernel_ram $mv_initrd_ram $mv_dtb_ram\0"\
|
|
"fitprep=imxtract $fitaddr kernel $mv_kernel_ram;"\
|
|
"imxtract $fitaddr ramdisk $mv_initrd_ram;"\
|
|
"imxtract $fitaddr fdt $mv_dtb_ram\0"\
|
|
"fdtprep=fdt addr $mv_dtb_ram;fdt boardsetup\0"\
|
|
"fitboot=run fitprep fdtprep addsqshrfs doboot\0"\
|
|
"i2c_init=run i2c_speed init_sdi_tx i2c_init_pll\0"\
|
|
"i2c_init_pll=i2c mw 65 9 2;i2c mw 65 9 0;i2c mw 65 5 2b;"\
|
|
"i2c mw 65 7 f;i2c mw 65 8 f;i2c mw 65 11 40;i2c mw 65 12 40;"\
|
|
"i2c mw 65 13 40; i2c mw 65 14 40; i2c mw 65 a 0\0"\
|
|
"i2c_speed=i2c dev 0;i2c speed 300000;i2c dev 1;i2c speed 120000\0"\
|
|
"init_sdi_tx=i2c mw 21 6 0;i2c mw 21 2 0;i2c mw 21 3 0;sleep 1;"\
|
|
"i2c mw 21 2 ff;i2c mw 21 3 3c\0"\
|
|
"splashimage=" __stringify(MV_SPLAH_ADDR) "\0"\
|
|
""
|
|
|
|
/*
|
|
* FPGA
|
|
*/
|
|
#define CONFIG_FPGA_COUNT 1
|
|
#define CONFIG_FPGA
|
|
#define CONFIG_FPGA_ALTERA
|
|
#define CONFIG_FPGA_CYCLON2
|
|
|
|
#endif
|
|
|