upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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497 lines
15 KiB
497 lines
15 KiB
/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian@popies.net>
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* Lead Tech Design <www.leadtechdesign.com>
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* Ilko Iliev <www.ronetix.at>
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*
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* (C) Copyright 2009
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* Eric Benard <eric@eukrea.com>
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*
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* Configuration settings for the Eukrea CPU9260 board.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* to be removed once maemory-map.h is fixed */
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#define AT91_BASE_SYS 0xffffe800
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#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
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#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
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#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
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#if defined(CONFIG_CPU9G20)
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#define CONFIG_AT91SAM9G20
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#elif defined(CONFIG_CPU9260)
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#define CONFIG_AT91SAM9260
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#else
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#error "Unknown board"
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#endif
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#include <asm/arch/hardware.h>
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#define CONFIG_ARCH_CPU_INIT
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#if defined(CONFIG_NANDBOOT)
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_SYS_TEXT_BASE 0x23f00000
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#else
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#define CONFIG_SYS_TEXT_BASE 0x00000000
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#endif
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/* clocks */
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#if defined(CONFIG_CPU9G20)
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#define MASTER_PLL_DIV 0x01
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#define MASTER_PLL_MUL 0x2B
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#elif defined(CONFIG_CPU9260)
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#define MASTER_PLL_DIV 0x09
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#define MASTER_PLL_MUL 0x61
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#endif
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/* CKGR_MOR - enable main osc. */
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#define CONFIG_SYS_MOR_VAL \
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(AT91_PMC_MOSCEN | \
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(255 << 8)) /* Main Oscillator Start-up Time */
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#if defined(CONFIG_CPU9G20)
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#define CONFIG_SYS_PLLAR_VAL \
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(AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
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((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
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#elif defined(CONFIG_CPU9260)
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#define CONFIG_SYS_PLLAR_VAL \
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(AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
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AT91_PMC_OUT | \
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((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
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#endif
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#if defined(CONFIG_CPU9G20)
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#define CONFIG_SYS_MCKR1_VAL \
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(AT91_PMC_CSS_PLLA | \
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AT91_PMC_PRES_1 | \
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AT91SAM9_PMC_MDIV_6 | \
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AT91_PMC_PDIV_2)
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#define CONFIG_SYS_MCKR2_VAL \
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CONFIG_SYS_MCKR1_VAL
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#elif defined(CONFIG_CPU9260)
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#define CONFIG_SYS_MCKR1_VAL \
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(AT91_PMC_CSS_SLOW | \
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AT91_PMC_PRES_1 | \
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AT91SAM9_PMC_MDIV_2 | \
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AT91_PMC_PDIV_1)
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#define CONFIG_SYS_MCKR2_VAL \
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(AT91_PMC_CSS_PLLA | \
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AT91_PMC_PRES_1 | \
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AT91SAM9_PMC_MDIV_2 | \
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AT91_PMC_PDIV_1)
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#endif
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/* define PDC[31:16] as DATA[31:16] */
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#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000
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/* no pull-up for D[31:16] */
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#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000
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/* EBI_CSA, 3.3V, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
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#define CONFIG_SYS_MATRIX_EBICSA_VAL \
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(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A | \
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AT91_MATRIX_CSA_EBI_CS3A | AT91_MATRIX_CSA_VDDIOMSEL_3_3V)
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/* SDRAM */
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/* SDRAMC_MR Mode register */
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#define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL
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/* SDRAMC_TR - Refresh Timer register */
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#define CONFIG_SYS_SDRC_TR_VAL1 0x287
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/* SDRAMC_CR - Configuration register*/
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#if defined(CONFIG_CPU9G20)
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#define CONFIG_SYS_SDRC_CR_VAL_64MB \
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(AT91_SDRAMC_NC_9 | \
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AT91_SDRAMC_NR_13 | \
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AT91_SDRAMC_NB_4 | \
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AT91_SDRAMC_CAS_2 | \
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AT91_SDRAMC_DBW_32 | \
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(2 << 8) | /* Write Recovery Delay */ \
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(9 << 12) | /* Row Cycle Delay */ \
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(3 << 16) | /* Row Precharge Delay */ \
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(3 << 20) | /* Row to Column Delay */ \
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(6 << 24) | /* Active to Precharge Delay */ \
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(10 << 28)) /* Exit Self Refresh to Active Delay */
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#define CONFIG_SYS_SDRC_CR_VAL_128MB \
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(AT91_SDRAMC_NC_10 | \
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AT91_SDRAMC_NR_13 | \
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AT91_SDRAMC_NB_4 | \
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AT91_SDRAMC_CAS_2 | \
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AT91_SDRAMC_DBW_32 | \
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(2 << 8) | /* Write Recovery Delay */ \
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(9 << 12) | /* Row Cycle Delay */ \
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(3 << 16) | /* Row Precharge Delay */ \
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(3 << 20) | /* Row to Column Delay */ \
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(6 << 24) | /* Active to Precharge Delay */ \
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(10 << 28)) /* Exit Self Refresh to Active Delay */
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#elif defined(CONFIG_CPU9260)
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#define CONFIG_SYS_SDRC_CR_VAL_64MB \
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(AT91_SDRAMC_NC_9 | \
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AT91_SDRAMC_NR_13 | \
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AT91_SDRAMC_NB_4 | \
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AT91_SDRAMC_CAS_2 | \
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AT91_SDRAMC_DBW_32 | \
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(2 << 8) | /* Write Recovery Delay */ \
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(7 << 12) | /* Row Cycle Delay */ \
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(2 << 16) | /* Row Precharge Delay */ \
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(2 << 20) | /* Row to Column Delay */ \
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(5 << 24) | /* Active to Precharge Delay */ \
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(8 << 28)) /* Exit Self Refresh to Active Delay */
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#define CONFIG_SYS_SDRC_CR_VAL_128MB \
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(AT91_SDRAMC_NC_10 | \
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AT91_SDRAMC_NR_13 | \
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AT91_SDRAMC_NB_4 | \
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AT91_SDRAMC_CAS_2 | \
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AT91_SDRAMC_DBW_32 | \
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(2 << 8) | /* Write Recovery Delay */ \
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(7 << 12) | /* Row Cycle Delay */ \
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(2 << 16) | /* Row Precharge Delay */ \
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(2 << 20) | /* Row to Column Delay */ \
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(5 << 24) | /* Active to Precharge Delay */ \
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(8 << 28)) /* Exit Self Refresh to Active Delay */
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#endif
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/* Memory Device Register -> SDRAM */
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#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
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#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
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#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
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#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
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#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
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#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
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#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
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/* setup SMC0, CS0 (NOR Flash) - 16-bit */
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#if defined(CONFIG_CPU9G20)
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#define CONFIG_SYS_SMC0_SETUP0_VAL \
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(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | \
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AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0))
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#define CONFIG_SYS_SMC0_PULSE0_VAL \
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(AT91_SMC_PULSE_NWE(8) | AT91_SMC_PULSE_NCS_WR(8) | \
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AT91_SMC_PULSE_NRD(14) | AT91_SMC_PULSE_NCS_RD(14))
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#define CONFIG_SYS_SMC0_CYCLE0_VAL \
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(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(14))
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#define CONFIG_SYS_SMC0_MODE0_VAL \
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(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
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AT91_SMC_MODE_DBW_16 | \
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AT91_SMC_MODE_TDF | \
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AT91_SMC_MODE_TDF_CYCLE(3))
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#elif defined(CONFIG_CPU9260)
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#define CONFIG_SYS_SMC0_SETUP0_VAL \
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(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | \
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AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0))
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#define CONFIG_SYS_SMC0_PULSE0_VAL \
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(AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(6) | \
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AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(10))
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#define CONFIG_SYS_SMC0_CYCLE0_VAL \
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(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(10))
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#define CONFIG_SYS_SMC0_MODE0_VAL \
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(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
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AT91_SMC_MODE_DBW_16 | \
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AT91_SMC_MODE_TDF | \
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AT91_SMC_MODE_TDF_CYCLE(2))
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#endif
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/* user reset enable */
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#define CONFIG_SYS_RSTC_RMR_VAL \
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(AT91_RSTC_KEY | \
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AT91_RSTC_CR_PROCRST | \
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AT91_RSTC_MR_ERSTL(1) | \
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AT91_RSTC_MR_ERSTL(2))
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/* Disable Watchdog */
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#define CONFIG_SYS_WDTC_WDMR_VAL \
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(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
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AT91_WDT_MR_WDV(0xfff) | \
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AT91_WDT_MR_WDDIS | \
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AT91_WDT_MR_WDD(0xfff))
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/*
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* Hardware drivers
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*/
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#define CONFIG_AT91SAM9_WATCHDOG
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#define CONFIG_AT91_GPIO
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#define CONFIG_ATMEL_USART
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#define CONFIG_USART_BASE ATMEL_BASE_DBGU
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#define CONFIG_USART_ID ATMEL_ID_SYS
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#define CONFIG_BOOTDELAY 3
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#undef CONFIG_CMD_BDI
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#undef CONFIG_CMD_IMI
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#undef CONFIG_CMD_FPGA
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#undef CONFIG_CMD_LOADS
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#undef CONFIG_CMD_IMLS
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_USB
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_MII
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/* SDRAM */
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_SDRAM_BASE 0x20000000
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#if defined(CONFIG_CPU9260_128M) || defined(CONFIG_CPU9G20_128M)
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#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
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#define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_128MB
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#else
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#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
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#define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_64MB
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#endif
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/* NAND flash */
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#define CONFIG_NAND_ATMEL
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE 0x40000000
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#define CONFIG_SYS_NAND_DBW_8 1
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#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PC(13)
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#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
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#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
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#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
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/* NOR flash */
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#if defined(CONFIG_NANDBOOT)
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#define CONFIG_SYS_NO_FLASH
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#else
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER
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#define PHYS_FLASH_1 0x10000000
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#define PHYS_FLASH_2 0x12000000
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#define CONFIG_SYS_FLASH_BANKS_LIST \
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{ PHYS_FLASH_1, PHYS_FLASH_2 }
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#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
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#define CONFIG_SYS_MAX_FLASH_SECT (255+4)
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#define CONFIG_SYS_MAX_FLASH_BANKS 2
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
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#define CONFIG_SYS_FLASH_PROTECTION
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#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
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#endif
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/* Ethernet */
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#define CONFIG_MACB
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#define CONFIG_RMII
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#define CONFIG_NET_RETRY_COUNT 20
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#define CONFIG_MACB_SEARCH_PHY
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#define CONFIG_AT91_WANTS_COMMON_PHY
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/* LEDS */
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/* Status LED */
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#define CONFIG_STATUS_LED
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#define CONFIG_BOARD_SPECIFIC_LED
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#define STATUS_LED_RED 0
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#define STATUS_LED_GREEN 1
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#define STATUS_LED_YELLOW 2
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#define STATUS_LED_BLUE 3
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/* Red */
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#define STATUS_LED_BIT STATUS_LED_RED
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#define STATUS_LED_STATE STATUS_LED_OFF
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#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
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/* Green */
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#define STATUS_LED_BIT1 STATUS_LED_GREEN
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#define STATUS_LED_STATE1 STATUS_LED_OFF
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#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
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/* Yellow */
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#define STATUS_LED_BIT2 STATUS_LED_YELLOW
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#define STATUS_LED_STATE2 STATUS_LED_OFF
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#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2)
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/* Blue */
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#define STATUS_LED_BIT3 STATUS_LED_BLUE
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#define STATUS_LED_STATE3 STATUS_LED_ON
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#define STATUS_LED_PERIOD3 (CONFIG_SYS_HZ / 2)
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/* Optional value */
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#define STATUS_LED_BOOT STATUS_LED_BIT
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#define CONFIG_RED_LED AT91_PIO_PORTC, 11
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#define CONFIG_GREEN_LED AT91_PIO_PORTC, 12
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#define CONFIG_YELLOW_LED AT91_PIO_PORTC, 7
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#define CONFIG_BLUE_LED AT91_PIO_PORTC, 9
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/* USB */
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#define CONFIG_USB_ATMEL
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#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
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#define CONFIG_USB_OHCI_NEW
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#define CONFIG_DOS_PARTITION
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#define CONFIG_SYS_USB_OHCI_CPU_INIT
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#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
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#if defined(CONFIG_CPU9G20)
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g20"
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#elif defined(CONFIG_CPU9260)
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
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#endif
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
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#define CONFIG_USB_STORAGE
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#define CONFIG_SYS_LOAD_ADDR 0x21000000
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#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END \
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(CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - 512 * 1024)
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#if defined(CONFIG_NANDBOOT)
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#define CONFIG_SYS_USE_NANDFLASH
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#undef CONFIG_SYS_USE_FLASH
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#else
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#define CONFIG_SYS_USE_FLASH
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#undef CONFIG_SYS_USE_NANDFLASH
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#endif
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#if defined(CONFIG_CPU9G20)
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#define CONFIG_SYS_BASEDIR "cpu9G20"
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#elif defined(CONFIG_CPU9260)
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#define CONFIG_SYS_BASEDIR "cpu9260"
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#endif
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#if defined(CONFIG_SYS_USE_FLASH)
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_OFFSET 0x40000
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#define CONFIG_ENV_SECT_SIZE 0x20000
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#define CONFIG_ENV_SIZE 0x20000
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_BOOTCOMMAND "run flashboot"
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#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=atmel_nand"
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#define MTDPARTS_DEFAULT \
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"mtdparts=physmap-flash.0:" \
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"256k(u-boot)ro," \
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"128k(u-boot-env)ro," \
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"1792k(kernel)," \
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"-(rootfs);" \
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"atmel_nand:-(nand)"
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#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 "
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"mtdids=" MTDIDS_DEFAULT "\0" \
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"mtdparts=" MTDPARTS_DEFAULT "\0" \
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"partition=nand0,0\0" \
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"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
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"ramboot=tftpboot 0x22000000 $(basedir)/uImage;" \
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"run ramargs;bootm 22000000\0" \
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"flashboot=run ramargs;bootm 0x10060000\0" \
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"basedir=" CONFIG_SYS_BASEDIR "\0" \
|
|
"updtub=tftp 0x24000000 $(basedir)/u-boot.bin;protect " \
|
|
"off 0x10000000 0x1003ffff;erase 0x10000000 " \
|
|
"0x1003ffff;cp.b 0x24000000 0x10000000 " \
|
|
"$(filesize)\0" \
|
|
"updtui=tftp 0x24000000 $(basedir)/uImage;protect off" \
|
|
" 0x10060000 0x1021ffff;erase 0x10060000 " \
|
|
"0x1021ffff;cp.b 0x24000000 0x10060000 " \
|
|
"$(filesize)\0" \
|
|
"updtrfs=tftp 0x24000000 $(basedir)/rootfs.jffs2; " \
|
|
"protect off 0x10220000 0x13ffffff;erase " \
|
|
"0x10220000 0x13ffffff;cp.b 0x24000000 " \
|
|
"0x10220000 $(filesize)\0" \
|
|
""
|
|
#elif defined(CONFIG_NANDBOOT)
|
|
#define CONFIG_ENV_IS_IN_NAND
|
|
#define CONFIG_ENV_OFFSET 0x60000
|
|
#define CONFIG_ENV_OFFSET_REDUND 0x80000
|
|
#define CONFIG_ENV_SECT_SIZE 0x20000
|
|
#define CONFIG_ENV_SIZE 0x20000
|
|
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
|
|
#define CONFIG_ENV_OVERWRITE
|
|
|
|
#define CONFIG_BOOTCOMMAND "run flashboot"
|
|
|
|
#define MTDIDS_DEFAULT "nand0=atmel_nand"
|
|
#define MTDPARTS_DEFAULT \
|
|
"mtdparts=atmel_nand:" \
|
|
"128k(bootstrap)ro," \
|
|
"256k(u-boot)ro," \
|
|
"128k(u-boot-env)ro," \
|
|
"128k(u-boot-env2)ro," \
|
|
"2M(kernel)," \
|
|
"-(rootfs)"
|
|
|
|
#define CONFIG_BOOTARGS "root=ubi0:eukrea-cpu9260-rootfs " \
|
|
"ubi.mtd=5 rootfstype=ubifs at91sam9_wdt.heartbeat=60"
|
|
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
"mtdids=" MTDIDS_DEFAULT "\0" \
|
|
"mtdparts=" MTDPARTS_DEFAULT "\0" \
|
|
"partition=nand0,5\0" \
|
|
"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
|
|
"ramboot=tftpboot 0x22000000 $(basedir)/uImage;" \
|
|
"run ramargs;bootm 22000000\0" \
|
|
"flashboot=run ramargs; nand read 0x22000000 0xA0000 " \
|
|
"0x200000; bootm 0x22000000\0" \
|
|
"basedir=" CONFIG_SYS_BASEDIR "\0" \
|
|
"u-boot=u-boot-eukrea-cpu9260.bin\0" \
|
|
"kernel=uImage-eukrea-cpu9260.bin\0" \
|
|
"rootfs=image-eukrea-cpu9260.ubi\0" \
|
|
"updtub=tftp ${loadaddr} $(basedir)/${u-boot}; " \
|
|
"nand erase 20000 40000; " \
|
|
"nand write ${loadaddr} 20000 40000\0" \
|
|
"updtui=tftp ${loadaddr} $(basedir)/${kernel}; " \
|
|
"nand erase a0000 200000; " \
|
|
"nand write ${loadaddr} a0000 200000\0" \
|
|
"updtrfs=tftp ${loadaddr} $(basedir)/${rootfs}; " \
|
|
"nand erase 2a0000 fd60000; " \
|
|
"nand write ${loadaddr} 2a0000 ${filesize}\0"
|
|
#endif
|
|
|
|
#define CONFIG_BAUDRATE 115200
|
|
|
|
#if defined(CONFIG_CPU9G20)
|
|
#define CONFIG_SYS_PROMPT "CPU9G20=> "
|
|
#elif defined(CONFIG_CPU9260)
|
|
#define CONFIG_SYS_PROMPT "CPU9260=> "
|
|
#endif
|
|
#define CONFIG_SYS_CBSIZE 256
|
|
#define CONFIG_SYS_MAXARGS 16
|
|
#define CONFIG_SYS_PBSIZE \
|
|
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
|
#define CONFIG_SYS_LONGHELP
|
|
#define CONFIG_CMDLINE_EDITING
|
|
#define CONFIG_SILENT_CONSOLE
|
|
#define CONFIG_NETCONSOLE
|
|
|
|
/*
|
|
* Size of malloc() pool
|
|
*/
|
|
#define CONFIG_SYS_MALLOC_LEN \
|
|
ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
|
|
|
|
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \
|
|
GENERATED_GBL_DATA_SIZE)
|
|
|
|
#endif
|
|
|