upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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126 lines
3.1 KiB
126 lines
3.1 KiB
/*
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* U-boot - Configuration file for Bluetechnix TCM-BF518 board
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*/
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#ifndef __CONFIG_TCM_BF518_H__
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#define __CONFIG_TCM_BF518_H__
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#include <asm/config-pre.h>
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/*
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* Processor Settings
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*/
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#define CONFIG_BFIN_CPU bf518-0.0
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#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
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/*
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* Clock Settings
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* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
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* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
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*/
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/* CONFIG_CLKIN_HZ is any value in Hz */
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#define CONFIG_CLKIN_HZ 25000000
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/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
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/* 1 = CLKIN / 2 */
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#define CONFIG_CLKIN_HALF 0
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/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
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/* 1 = bypass PLL */
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#define CONFIG_PLL_BYPASS 0
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/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
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/* Values can range from 0-63 (where 0 means 64) */
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#define CONFIG_VCO_MULT 16
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/* CCLK_DIV controls the core clock divider */
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/* Values can be 1, 2, 4, or 8 ONLY */
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#define CONFIG_CCLK_DIV 1
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/* SCLK_DIV controls the system clock divider */
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/* Values can range from 1-15 */
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#define CONFIG_SCLK_DIV 4
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/*
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* Memory Settings
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*/
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/* This board has a 32meg MT48H16M16 */
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#define CONFIG_MEM_ADD_WDTH 9
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#define CONFIG_MEM_SIZE 32
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#define CONFIG_EBIU_SDRRC_VAL 0x3f8
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#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
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#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL)
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#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
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#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
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#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
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/*
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* Network Settings
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*/
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#if !defined(__ADSPBF512__) && !defined(__ADSPBF514__)
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#define ADI_CMDS_NETWORK 1
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#define CONFIG_BFIN_MAC
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#define CONFIG_NETCONSOLE 1
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#endif
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#define CONFIG_HOSTNAME tcm-bf518
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/* Uncomment next line to use fixed MAC address */
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/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
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#define CONFIG_LIB_RAND
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/*
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* Flash Settings
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*/
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_BASE 0x20000000
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_PROTECTION
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 19
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/*
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* SPI Settings
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*/
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#define CONFIG_BFIN_SPI
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#define CONFIG_ENV_SPI_MAX_HZ 30000000
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#define CONFIG_SF_DEFAULT_SPEED 30000000
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/*
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* Env Storage Settings
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*/
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_OFFSET 0x8000
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_SECT_SIZE 0x8000
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#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
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/*
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* I2C Settings
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*/
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#define CONFIG_BFIN_TWI_I2C 1
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#define CONFIG_HARD_I2C 1
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/*
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* Misc Settings
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*/
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_MISC_INIT_R
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#define CONFIG_RTC_BFIN
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#define CONFIG_UART_CONSOLE 0
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#define CONFIG_BOOTCOMMAND "run flashboot"
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#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0"
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#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
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/*
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* Pull in common ADI header for remaining command/environment setup
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*/
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#include <configs/bfin_adi_common.h>
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#endif
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