upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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272 lines
9.0 KiB
272 lines
9.0 KiB
/*
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* (C) Copyright 2011 HALE electronic <helmut.raiger@hale.at>
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* (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
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*
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* Configuration settings for the HALE TT-01 board.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <asm/arch/imx-regs.h>
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/* High Level Configuration Options */
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#define CONFIG_ARM1136
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#define CONFIG_MX31
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_MACH_TYPE 3726 /* not yet in mach-types.h */
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#define CONFIG_SYS_TEXT_BASE 0xA0000000
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/*
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* Physical Memory Map:
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* CS settings are defined by i.MX31:
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* - CSD0 and CDS1 are 256MB each, starting at 0x80000000 and 0x9000000
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* - CS0 and CS1 are 128MB each, at A0000000 and A8000000
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* - CS2 to CS5 are 32MB each, at B0.., B2.., B4.., B6..
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*
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* HALE set-up of the bluetechnix board for now is:
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* - 128MB DDR (2x64MB, 2x16bit), connected to 32bit DDR ram interface
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* - NOR-Flash (Spansion 32MB MCP, Flash+16MB PSRAM), 16bit interface at CS0
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* - S71WS256ND0BFWYM (and CS1 for 64MB S71WS512ND0 without PSRAM)
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* the flash chip is a mirrorbit S29WS256N !
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* - the PSRAM is hooked to CS5 (0xB6000000)
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* - Intel Strata Flash PF48F2000P0ZB00, 16bit interface at (CS0 or) CS1
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* - 64Mbit = 8MByte (will go away in the production set-up)
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* - NAND-Flash NAND01GR3B2BZA6 at NAND-FC:
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* 1Gbit=128MB, 2048+64 bytes/page, 64pages x 1024 blocks
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* - Ethernet controller SMC9118 at CS4 via FPGA, 16bit interface
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*
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* u-boot will support the 32MB nor flash and the 128MB NAND flash, the PSRAM
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* is not used right now. We should be able to reduce the SOM to NAND flash
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* only and boot from there.
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*/
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM_1 CSD0_BASE
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#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_BOARD_LATE_INIT
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
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#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
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/* default load address, 1MB up the road */
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#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1+0x100000)
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/* Size of malloc() pool, make sure possible frame buffer fits */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 10*1024*1024)
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/* memtest works on all but the last 1MB (u-boot) and malloc area */
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#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
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#define CONFIG_SYS_MEMTEST_END \
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(PHYS_SDRAM_1+(PHYS_SDRAM_1_SIZE-CONFIG_SYS_MALLOC_LEN-0x100000))
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/* CFI FLASH driver setup */
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#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
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#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */
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#define CONFIG_FLASH_SPANSION_S29WS_N
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/*
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* TODO: Bluetechnix (the supplier of the SOM) did define these values
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* in their original version of u-boot (1.2 or so). This should be
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* reviewed.
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*
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* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
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* #define CONFIG_SYS_FLASH_PROTECTION
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*/
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#define CONFIG_SYS_FLASH_BASE CS0_BASE
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT (254+8) /* max number of sectors per chip */
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/*
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* FLASH and environment organization, only the Spansion chip is supported:
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* - it has 254 * 128kB + 8 * 32kB blocks
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* - this setup uses 4*32k+3*128k as monitor space = 0xA000 0000 to 0xA00F FFFF
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* and 2 sectors with 128k as environment =
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* A010 0000 to 0xA011 FFFF and 0xA012 0000 to 0xA013 FFFF
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* - this could be less, but this is only for developer versions of the board
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* and no-one is going to use the NOR flash anyway.
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*
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* Monitor is at the beginning of the NOR-Flash, 1MB reserved. Again this is
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* way to large, but it avoids ENV overwrite (when updating u-boot) in case
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* size breaks the next boundary (as it has with 128k).
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*/
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SECT_SIZE (128 * 1024)
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#define CONFIG_ENV_SIZE (128 * 1024)
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/* Address and size of Redundant Environment Sector */
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#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
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#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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/* Hardware drivers */
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/*
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* on TT-01 UART1 pins are used by Audio, so we use UART2
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* TT-01 implements a hardware that turns off components depending on
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* the power level. In PL=1 the RS232 transceiver is usually off,
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* make sure that the transceiver is enabled during PL=1 for testing!
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*/
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#define CONFIG_MXC_UART
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#define CONFIG_MXC_UART_BASE UART2_BASE
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#define CONFIG_MXC_SPI
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#define CONFIG_MXC_GPIO
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/* MC13783 connected to CSPI3 and SS0 */
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#define CONFIG_POWER
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#define CONFIG_POWER_SPI
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#define CONFIG_POWER_FSL
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#define CONFIG_FSL_PMIC_BUS 2
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#define CONFIG_FSL_PMIC_CS 0
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#define CONFIG_FSL_PMIC_CLK 1000000
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#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
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#define CONFIG_FSL_PMIC_BITLEN 32
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#define CONFIG_RTC_MC13XXX
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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/* console is UART2 on TT-01 */
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_BAUDRATE 115200
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/* ethernet setup for the onboard smc9118 */
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#define CONFIG_MII
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#define CONFIG_SMC911X
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/* 16 bit, onboard ethernet, decoded via MACH-MX0 FPGA at 0x84200000 */
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#define CONFIG_SMC911X_BASE (CS4_BASE+0x200000)
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#define CONFIG_SMC911X_16_BIT
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/* mmc driver */
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#define CONFIG_MMC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_MXC_MMC
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#define CONFIG_MXC_MCI_REGS_BASE SDHC1_BASE_ADDR
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/* video support */
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#define CONFIG_VIDEO
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#define CONFIG_VIDEO_MX3
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#define CONFIG_CFB_CONSOLE
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#define CONFIG_VIDEO_LOGO
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/* splash image won't work with NAND boot, use preboot script */
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#define CONFIG_VIDEO_SW_CURSOR
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#define CONFIG_CONSOLE_EXTRA_INFO /* display additional board info */
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#define CONFIG_VGA_AS_SINGLE_DEVICE /* display is an output only device */
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/* allow stdin, stdout and stderr variables to redirect output */
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV
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#define CONFIG_SILENT_CONSOLE /* UARTs used externally (release) */
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#define CONFIG_SYS_DEVICE_NULLDEV /* allow console to be turned off */
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#define CONFIG_PREBOOT
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/* allow decompressing max. 4MB */
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#define CONFIG_VIDEO_BMP_GZIP
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/* this is not only used by cfb_console.c for the logo, but also in cmd_bmp.c */
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#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (4*1024*1024)
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/*
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* Command definition
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_SAVEENV
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#define CONFIG_CMD_NAND
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/*
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* #define CONFIG_CMD_NAND_LOCK_UNLOCK the NAND01... chip does not support
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* the NAND_CMD_LOCK_STATUS command, however the NFC of i.MX31 supports
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* a software locking scheme.
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*/
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#define CONFIG_CMD_BMP
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#define CONFIG_BOOTDELAY 3
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/*
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* currently a default setting for booting via script is implemented
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* set user to login name and serverip to tftp host, define your
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* boot behaviour in bootscript.loginname
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*
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* TT-01 board specific TFT setup (used by drivers/video/mx3fb.c)
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*
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* This set-up is for the L5F30947T04 by Epson, which is
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* 800x480, 33MHz pixel clock, 60Hz vsync, 31.6kHz hsync
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* sync must be set to: DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL
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*/
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"videomode=epson\0" \
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"epson=video=ctfb:x:800,y:480,depth:16,mode:0,pclk:30076," \
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"le:215,ri:1,up:32,lo:13,hs:7,vs:10,sync:100663296,vmode:0\0" \
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"bootcmd=dhcp bootscript.${user}; source\0"
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#define CONFIG_BOOTP_SERVERIP /* tftp serverip not overruled by dhcp server */
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#define CONFIG_BOOTP_SEND_HOSTNAME /* if env-var 'hostname' is set, send it */
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "TT01> "
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT)+16)
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/* max number of command args */
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#define CONFIG_SYS_MAXARGS 16
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_CMDLINE_EDITING
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/* MMC boot support */
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#define CONFIG_CMD_MMC
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#define CONFIG_DOS_PARTITION
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#define CONFIG_EFI_PARTITION
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_FAT
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#define CONFIG_NAND_MXC
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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/*
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* actually this is nothing someone wants to configure!
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* CONFIG_SYS_NAND_BASE despite being passed to board_nand_init()
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* is not used by the driver.
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*/
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#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR
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#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
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#define CONFIG_MXC_NAND_HWECC
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/* the current u-boot driver does not use the nand flash setup! */
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#define CONFIG_SYS_NAND_LARGEPAGE
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/*
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* it's not 16 bit:
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* #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
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* the current u-boot mxc_nand.c tries to auto-detect, but this only
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* reads the boot settings during reset (which might be wrong)
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*/
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#endif /* __CONFIG_H */
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