upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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424 lines
15 KiB
424 lines
15 KiB
/*
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* (C) Copyright 2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/************************************************************************
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* acadia.h - configuration for AMCC Acadia (405EZ)
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***********************************************************************/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*-----------------------------------------------------------------------
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* High Level Configuration Options
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*----------------------------------------------------------------------*/
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#define CONFIG_ACADIA 1 /* Board is Acadia */
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#define CONFIG_4xx 1 /* ... PPC4xx family */
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#define CONFIG_405EZ 1 /* Specifc 405EZ support*/
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#undef CFG_DRAM_TEST /* Disable-takes long time */
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#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
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#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
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#define CONFIG_NO_SERIAL_EEPROM
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/*#undef CONFIG_NO_SERIAL_EEPROM*/
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#ifdef CONFIG_NO_SERIAL_EEPROM
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/*----------------------------------------------------------------------------
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* PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
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* assuming a 66MHz input clock to the 405EZ.
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*---------------------------------------------------------------------------*/
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/* #define PLLMR0_100_100_12 */
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#define PLLMR0_200_133_66
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/* #define PLLMR0_266_160_80 */
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/* #define PLLMR0_333_166_83 */
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#endif
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/*-----------------------------------------------------------------------
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*----------------------------------------------------------------------*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_FLASH_BASE 0xFE000000
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#define CFG_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Monitor */
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#define CFG_MALLOC_LEN (384 * 1024)/* Reserve 128 kB for malloc() */
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#define CFG_MONITOR_BASE TEXT_BASE
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#define CFG_USB_HOST 0xef603000 /* USB OHCI 1.1 controller */
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/*
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* Define here the location of the environment variables (FLASH).
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* Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
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* supported for backward compatibility.
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*/
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#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
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#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
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#else
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#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
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#endif
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#define CONFIG_PREBOOT "echo;" \
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"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
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"echo"
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#undef CONFIG_BOOTARGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"hostname=acadia\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
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"flash_nfs=run nfsargs addip addtty;" \
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"bootm ${kernel_addr}\0" \
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"flash_self=run ramargs addip addtty;" \
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"bootm ${kernel_addr} ${ramdisk_addr}\0" \
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"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
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"bootm\0" \
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"rootpath=/opt/eldk/ppc_4xx\0" \
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"bootfile=acadia/uImage\0" \
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"kernel_addr=fff10000\0" \
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"ramdisk_addr=fff20000\0" \
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"initrd_high=30000000\0" \
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"load=tftp 200000 acadia/u-boot.bin\0" \
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"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
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"cp.b ${fileaddr} fffc0000 ${filesize};" \
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"setenv filesize;saveenv\0" \
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"upd=run load;run update\0" \
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"kozio=bootm ffc60000\0" \
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""
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#define CONFIG_BOOTCOMMAND "run flash_self"
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#if 0
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
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#else
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#endif
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 0 /* PHY address */
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#define CONFIG_NET_MULTI 1
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#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
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#define CONFIG_NETCONSOLE /* include NetConsole support */
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#define CONFIG_USB_OHCI
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#define CONFIG_USB_STORAGE
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#if 0 /* test-only */
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#define TEST_ONLY_NAND
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#endif
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#ifdef TEST_ONLY_NAND
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#define CMD_NAND CFG_CMD_NAND
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#else
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#define CMD_NAND 0
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#endif
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/* Partitions */
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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#define CONFIG_ISO_PARTITION
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#define CONFIG_SUPPORT_VFAT
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
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CFG_CMD_ASKENV | \
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CFG_CMD_DHCP | \
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CFG_CMD_DTT | \
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CFG_CMD_DIAG | \
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CFG_CMD_EEPROM | \
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CFG_CMD_ELF | \
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CFG_CMD_FAT | \
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CFG_CMD_I2C | \
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CFG_CMD_IRQ | \
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CFG_CMD_MII | \
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CMD_NAND | \
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CFG_CMD_NET | \
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CFG_CMD_NFS | \
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CFG_CMD_PCI | \
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CFG_CMD_PING | \
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CFG_CMD_REGINFO | \
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CFG_CMD_SDRAM | \
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CFG_CMD_USB)
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
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#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
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#define CONFIG_LOOPW 1 /* enable loopw command */
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#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
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#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
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/*-----------------------------------------------------------------------
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* Serial Port
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*----------------------------------------------------------------------*/
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#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
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#define CFG_BASE_BAUD 691200
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#define CONFIG_BAUDRATE 115200
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/* The following table includes the supported baudrates */
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#define CFG_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
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/*-----------------------------------------------------------------------
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* I2C
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*----------------------------------------------------------------------*/
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_MULTI_EEPROMS
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#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
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#define CFG_I2C_EEPROM_ADDR_LEN 1
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#define CFG_EEPROM_PAGE_WRITE_ENABLE
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#define CFG_EEPROM_PAGE_WRITE_BITS 3
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
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/* I2C SYSMON (LM75, AD7414 is almost compatible) */
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#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
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#define CONFIG_DTT_AD7414 1 /* use AD7414 */
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#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
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#define CFG_DTT_MAX_TEMP 70
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#define CFG_DTT_LOW_TEMP -30
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#define CFG_DTT_HYSTERESIS 3
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#if 0 /* test-only... */
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/*-----------------------------------------------------------------------
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* SPI stuff - Define to include SPI control
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_SPI
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#endif
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH related
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*----------------------------------------------------------------------*/
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#define CFG_FLASH_CFI
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#define CFG_FLASH_CFI_DRIVER
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#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
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#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
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#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
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#define CFG_MAX_FLASH_SECT 1024 /* sectors per device */
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#undef CFG_FLASH_CHECKSUM
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#ifdef CFG_ENV_IS_IN_FLASH
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#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
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/* Address and size of Redundant Environment Sector */
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#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
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#endif
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#ifdef TEST_ONLY_NAND
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/*-----------------------------------------------------------------------
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* NAND FLASH
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*----------------------------------------------------------------------*/
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#define CFG_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS 1
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#define CFG_NAND_BASE (CFG_NAND + CFG_NAND_CS)
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#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
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#endif
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_DCACHE_SIZE 16384 /* For AMCC 405EZ CPU */
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#define CFG_CACHELINE_SIZE 32 /* ... */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/
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#endif
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in data cache)
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*/
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/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
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#define CFG_TEMP_STACK_OCM 1
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/* On Chip Memory location */
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#define CFG_OCM_DATA_ADDR 0xF8000000
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#define CFG_OCM_DATA_SIZE 0x4000 /* 16K of onchip SRAM */
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#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SRAM */
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#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
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#define CFG_GBL_DATA_SIZE 128 /* size for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* External Bus Controller (EBC) Setup
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*/
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#define CFG_NAND 0xd0000000
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#define CFG_NAND_CS 0 /* NAND chip connected to CSx */
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/* Memory Bank 0 (Flash) initialization */
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#define CFG_EBC_PB0AP 0x03337200
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#define CFG_EBC_PB0CR 0xfe0bc000 /* BAS=0xFE0,BS=32MB,BU=R/W,BW=32bit */
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/* Memory Bank 1 (CRAM) initialization */
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#define CFG_EBC_PB1AP 0x030400c0
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#define CFG_EBC_PB1CR 0x000bc000
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/* Memory Bank 2 (CRAM) initialization */
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#define CFG_EBC_PB2AP 0x030400c0
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#define CFG_EBC_PB2CR 0x020bc000
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/* Memory Bank 3 (NAND-FLASH) initialization */
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#define CFG_EBC_PB3AP 0x018003c0
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#define CFG_EBC_PB3CR (CFG_NAND | 0x1c000)
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/* Memory Bank 4 (CPLD) initialization */
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#define CFG_EBC_PB4AP 0x04006000
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#define CFG_EBC_PB4CR 0x80018000 /* BAS=0x000,BS=16MB,BU=R/W,BW=32bit */
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#define CFG_EBC_CFG 0xf8400000
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/*-----------------------------------------------------------------------
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* Definitions for GPIO_0 setup (PPC405EZ specific)
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*
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* GPIO0[0-3] - External Bus Controller CS_4 - CS_7 Outputs
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* GPIO0[4] - External Bus Controller Hold Input
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* GPIO0[5] - External Bus Controller Priority Input
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* GPIO0[6] - External Bus Controller HLDA Output
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* GPIO0[7] - External Bus Controller Bus Request Output
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* GPIO0[8] - CRAM Clk Output
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* GPIO0[9] - External Bus Controller Ready Input
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* GPIO0[10] - CRAM Adv Output
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* GPIO0[11-24] - NAND Flash Control Data -> Bypasses GPIO when enabled
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* GPIO0[25] - External DMA Request Input
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* GPIO0[26] - External DMA EOT I/O
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* GPIO0[25] - External DMA Ack_n Output
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* GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
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* GPIO0[28-30] - Trace Outputs / PWM Inputs
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* GPIO0[31] - PWM_8 I/O
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*/
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#define CFG_GPIO0_TCR 0xC0000000
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#define CFG_GPIO0_OSRL 0x50000000
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#define CFG_GPIO0_OSRH 0x00000055
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#define CFG_GPIO0_ISR1L 0x00000000
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#define CFG_GPIO0_ISR1H 0x00000055
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#define CFG_GPIO0_TSRL 0x00000000
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#define CFG_GPIO0_TSRH 0x00000055
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/*-----------------------------------------------------------------------
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* Definitions for GPIO_1 setup (PPC405EZ specific)
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*
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* GPIO1[0-6] - PWM_9 to PWM_15 I/O
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* GPIO1[7] - PWM_DIV_CLK (Out) / IRQ4 Input
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* GPIO1[8] - TS5 Output / DAC_IP_TRIG Input
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* GPIO1[9] - TS6 Output / ADC_IP_TRIG Input
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* GPIO1[10-12] - UART0 Control Inputs
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* GPIO1[13] - UART0_DTR_N Output/IEEE_1588_TS Output/TMRCLK Input
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* GPIO1[14] - UART0_RTS_N Output/SPI_SS_2_N Output
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* GPIO1[15] - SPI_SS_3_N Output/UART0_RI_N Input
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* GPIO1[16] - SPI_SS_1_N Output
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* GPIO1[17-20] - Trace Output/External Interrupts IRQ0 - IRQ3 inputs
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*/
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#define CFG_GPIO1_OSRH 0x55455555
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#define CFG_GPIO1_OSRL 0x40000110
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#define CFG_GPIO1_ISR1H 0x00000000
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#define CFG_GPIO1_ISR1L 0x15555445
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#define CFG_GPIO1_TSRH 0x00000000
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#define CFG_GPIO1_TSRL 0x00000000
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#define CFG_GPIO1_TCR 0xFFFF8014
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/*-----------------------------------------------------------------------
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* EPLD Regs.
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*/
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#define EPLD_BASE 0x80000000
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#define EPLD_ETHRSTBOOT 0x10
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#define EPLD_CTRL 0x14
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#define EPLD_MUXOE 0x16
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/*
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* State definations
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*/
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#define LOAK_INIT 0x494e4954 /* ASCII "INIT" */
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#define LOAK_NONE 0x4e4f4e45 /* ASCII "NONE" */
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#define LOAK_CRAM 0x4352414d /* ASCII "CRAM" */
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#define LOAK_PSRAM 0x50535241 /* ASCII "PSRA" - PSRAM */
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#define LOAK_OCM 0x4f434d20 /* ASCII "OCM " */
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#define LOAK_ZERO 0x5a45524f /* ASCII "ZERO" */
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#define LOAK_SPL 0x53504c20 /* ASCII "SPL" */
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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#endif /* __CONFIG_H */
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