upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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69 lines
2.1 KiB
69 lines
2.1 KiB
/*
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* (C) Copyright 2002
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* Daniel Engström, Omicron Ceti AB, daniel@omicron.se
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _PCI_I386_H_
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#define _PCI_I386_H_
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#include <pci.h>
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/* bus mapping constants (used for PCI core initialization) */
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#define PCI_REG_ADDR 0xcf8
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#define PCI_REG_DATA 0xcfc
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#define PCI_CFG_EN 0x80000000
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#ifndef __ASSEMBLY__
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#define DEFINE_PCI_DEVICE_TABLE(_table) \
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const struct pci_device_id _table[]
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struct pci_controller;
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void pci_setup_type1(struct pci_controller *hose);
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/**
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* board_pci_setup_hose() - Set up the PCI hose
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*
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* This is called by the common x86 PCI code to set up the PCI controller
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* hose. It may be called when no memory/BSS is available so should just
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* store things in 'hose' and not in BSS variables.
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*/
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void board_pci_setup_hose(struct pci_controller *hose);
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/**
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* pci_early_init_hose() - Set up PCI host before relocation
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*
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* This allocates memory for, sets up and returns the PCI hose. It can be
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* called before relocation. The hose will be stored in gd->hose for
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* later use, but will become invalid one DRAM is available.
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*/
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int pci_early_init_hose(struct pci_controller **hosep);
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int board_pci_pre_scan(struct pci_controller *hose);
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int board_pci_post_scan(struct pci_controller *hose);
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/*
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* Simple PCI access routines - these work from either the early PCI hose
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* or the 'real' one, created after U-Boot has memory available
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*/
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unsigned int x86_pci_read_config8(pci_dev_t dev, unsigned where);
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unsigned int x86_pci_read_config16(pci_dev_t dev, unsigned where);
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unsigned int x86_pci_read_config32(pci_dev_t dev, unsigned where);
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void x86_pci_write_config8(pci_dev_t dev, unsigned where, unsigned value);
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void x86_pci_write_config16(pci_dev_t dev, unsigned where, unsigned value);
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void x86_pci_write_config32(pci_dev_t dev, unsigned where, unsigned value);
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int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset,
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ulong *valuep, enum pci_size_t size);
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int pci_x86_write_config(struct udevice *bus, pci_dev_t bdf, uint offset,
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ulong value, enum pci_size_t size);
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#endif /* __ASSEMBLY__ */
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#endif /* _PCI_I386_H_ */
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