upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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315 lines
7.7 KiB
315 lines
7.7 KiB
/*
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* Copyright (C) 2014 Google, Inc
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*
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* From coreboot, originally based on the Linux kernel (drivers/pci/pci.c).
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*
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* Modifications are:
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* Copyright (C) 2003-2004 Linux Networx
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* (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
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* Copyright (C) 2003-2006 Ronald G. Minnich <rminnich@gmail.com>
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* Copyright (C) 2004-2005 Li-Ta Lo <ollie@lanl.gov>
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* Copyright (C) 2005-2006 Tyan
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* (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
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* Copyright (C) 2005-2009 coresystems GmbH
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* (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
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*
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* PCI Bus Services, see include/linux/pci.h for further explanation.
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*
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* Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
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* David Mosberger-Tang
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*
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* Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <bios_emul.h>
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#include <errno.h>
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#include <malloc.h>
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#include <pci.h>
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#include <pci_rom.h>
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#include <vbe.h>
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#include <video_fb.h>
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#ifdef CONFIG_HAVE_ACPI_RESUME
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#include <asm/acpi.h>
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#endif
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__weak bool board_should_run_oprom(pci_dev_t dev)
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{
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return true;
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}
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static bool should_load_oprom(pci_dev_t dev)
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{
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#ifdef CONFIG_HAVE_ACPI_RESUME
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if (acpi_get_slp_type() == 3)
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return false;
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#endif
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if (IS_ENABLED(CONFIG_ALWAYS_LOAD_OPROM))
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return 1;
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if (board_should_run_oprom(dev))
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return 1;
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return 0;
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}
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__weak uint32_t board_map_oprom_vendev(uint32_t vendev)
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{
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return vendev;
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}
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static int pci_rom_probe(pci_dev_t dev, uint class,
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struct pci_rom_header **hdrp)
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{
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struct pci_rom_header *rom_header;
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struct pci_rom_data *rom_data;
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u16 vendor, device;
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u16 rom_vendor, rom_device;
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u32 rom_class;
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u32 vendev;
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u32 mapped_vendev;
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u32 rom_address;
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pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
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pci_read_config_word(dev, PCI_DEVICE_ID, &device);
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vendev = vendor << 16 | device;
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mapped_vendev = board_map_oprom_vendev(vendev);
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if (vendev != mapped_vendev)
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debug("Device ID mapped to %#08x\n", mapped_vendev);
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#ifdef CONFIG_X86_OPTION_ROM_ADDR
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rom_address = CONFIG_X86_OPTION_ROM_ADDR;
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#else
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if (pciauto_setup_rom(pci_bus_to_hose(PCI_BUS(dev)), dev)) {
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debug("Cannot find option ROM\n");
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return -ENOENT;
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}
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pci_read_config_dword(dev, PCI_ROM_ADDRESS, &rom_address);
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if (rom_address == 0x00000000 || rom_address == 0xffffffff) {
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debug("%s: rom_address=%x\n", __func__, rom_address);
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return -ENOENT;
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}
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/* Enable expansion ROM address decoding. */
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pci_write_config_dword(dev, PCI_ROM_ADDRESS,
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rom_address | PCI_ROM_ADDRESS_ENABLE);
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#endif
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debug("Option ROM address %x\n", rom_address);
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rom_header = (struct pci_rom_header *)(unsigned long)rom_address;
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debug("PCI expansion ROM, signature %#04x, INIT size %#04x, data ptr %#04x\n",
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le16_to_cpu(rom_header->signature),
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rom_header->size * 512, le16_to_cpu(rom_header->data));
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if (le16_to_cpu(rom_header->signature) != PCI_ROM_HDR) {
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printf("Incorrect expansion ROM header signature %04x\n",
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le16_to_cpu(rom_header->signature));
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return -EINVAL;
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}
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rom_data = (((void *)rom_header) + le16_to_cpu(rom_header->data));
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rom_vendor = le16_to_cpu(rom_data->vendor);
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rom_device = le16_to_cpu(rom_data->device);
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debug("PCI ROM image, vendor ID %04x, device ID %04x,\n",
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rom_vendor, rom_device);
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/* If the device id is mapped, a mismatch is expected */
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if ((vendor != rom_vendor || device != rom_device) &&
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(vendev == mapped_vendev)) {
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printf("ID mismatch: vendor ID %04x, device ID %04x\n",
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rom_vendor, rom_device);
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/* Continue anyway */
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}
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rom_class = (le16_to_cpu(rom_data->class_hi) << 8) | rom_data->class_lo;
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debug("PCI ROM image, Class Code %06x, Code Type %02x\n",
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rom_class, rom_data->type);
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if (class != rom_class) {
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debug("Class Code mismatch ROM %06x, dev %06x\n",
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rom_class, class);
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}
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*hdrp = rom_header;
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return 0;
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}
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int pci_rom_load(struct pci_rom_header *rom_header,
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struct pci_rom_header **ram_headerp)
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{
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struct pci_rom_data *rom_data;
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unsigned int rom_size;
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unsigned int image_size = 0;
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void *target;
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do {
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/* Get next image, until we see an x86 version */
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rom_header = (struct pci_rom_header *)((void *)rom_header +
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image_size);
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rom_data = (struct pci_rom_data *)((void *)rom_header +
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le16_to_cpu(rom_header->data));
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image_size = le16_to_cpu(rom_data->ilen) * 512;
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} while ((rom_data->type != 0) && (rom_data->indicator == 0));
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if (rom_data->type != 0)
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return -EACCES;
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rom_size = rom_header->size * 512;
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#ifdef PCI_VGA_RAM_IMAGE_START
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target = (void *)PCI_VGA_RAM_IMAGE_START;
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#else
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target = (void *)malloc(rom_size);
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if (!target)
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return -ENOMEM;
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#endif
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if (target != rom_header) {
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ulong start = get_timer(0);
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debug("Copying VGA ROM Image from %p to %p, 0x%x bytes\n",
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rom_header, target, rom_size);
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memcpy(target, rom_header, rom_size);
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if (memcmp(target, rom_header, rom_size)) {
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printf("VGA ROM copy failed\n");
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return -EFAULT;
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}
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debug("Copy took %lums\n", get_timer(start));
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}
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*ram_headerp = target;
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return 0;
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}
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static struct vbe_mode_info mode_info;
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int vbe_get_video_info(struct graphic_device *gdev)
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{
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#ifdef CONFIG_FRAMEBUFFER_SET_VESA_MODE
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struct vesa_mode_info *vesa = &mode_info.vesa;
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gdev->winSizeX = vesa->x_resolution;
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gdev->winSizeY = vesa->y_resolution;
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gdev->plnSizeX = vesa->x_resolution;
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gdev->plnSizeY = vesa->y_resolution;
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gdev->gdfBytesPP = vesa->bits_per_pixel / 8;
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switch (vesa->bits_per_pixel) {
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case 24:
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gdev->gdfIndex = GDF_32BIT_X888RGB;
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break;
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case 16:
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gdev->gdfIndex = GDF_16BIT_565RGB;
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break;
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default:
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gdev->gdfIndex = GDF__8BIT_INDEX;
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break;
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}
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gdev->isaBase = CONFIG_SYS_ISA_IO_BASE_ADDRESS;
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gdev->pciBase = vesa->phys_base_ptr;
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gdev->frameAdrs = vesa->phys_base_ptr;
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gdev->memSize = vesa->bytes_per_scanline * vesa->y_resolution;
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gdev->vprBase = vesa->phys_base_ptr;
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gdev->cprBase = vesa->phys_base_ptr;
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return gdev->winSizeX ? 0 : -ENOSYS;
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#else
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return -ENOSYS;
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#endif
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}
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int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), int exec_method)
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{
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struct pci_rom_header *rom, *ram;
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int vesa_mode = -1;
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uint class;
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bool emulate;
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int ret;
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/* Only execute VGA ROMs */
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pci_read_config_dword(dev, PCI_REVISION_ID, &class);
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if (((class >> 16) ^ PCI_CLASS_DISPLAY_VGA) & 0xff00) {
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debug("%s: Class %#x, should be %#x\n", __func__, class,
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PCI_CLASS_DISPLAY_VGA);
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return -ENODEV;
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}
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class >>= 8;
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if (!should_load_oprom(dev))
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return -ENXIO;
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ret = pci_rom_probe(dev, class, &rom);
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if (ret)
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return ret;
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ret = pci_rom_load(rom, &ram);
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if (ret)
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return ret;
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if (!board_should_run_oprom(dev))
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return -ENXIO;
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#if defined(CONFIG_FRAMEBUFFER_SET_VESA_MODE) && \
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defined(CONFIG_FRAMEBUFFER_VESA_MODE)
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vesa_mode = CONFIG_FRAMEBUFFER_VESA_MODE;
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#endif
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debug("Selected vesa mode %#x\n", vesa_mode);
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if (exec_method & PCI_ROM_USE_NATIVE) {
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#ifdef CONFIG_X86
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emulate = false;
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#else
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if (!(exec_method & PCI_ROM_ALLOW_FALLBACK)) {
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printf("BIOS native execution is only available on x86\n");
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return -ENOSYS;
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}
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emulate = true;
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#endif
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} else {
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#ifdef CONFIG_BIOSEMU
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emulate = true;
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#else
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if (!(exec_method & PCI_ROM_ALLOW_FALLBACK)) {
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printf("BIOS emulation not available - see CONFIG_BIOSEMU\n");
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return -ENOSYS;
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}
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emulate = false;
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#endif
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}
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if (emulate) {
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#ifdef CONFIG_BIOSEMU
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BE_VGAInfo *info;
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ret = biosemu_setup(dev, &info);
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if (ret)
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return ret;
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biosemu_set_interrupt_handler(0x15, int15_handler);
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ret = biosemu_run(dev, (uchar *)ram, 1 << 16, info, true,
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vesa_mode, &mode_info);
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if (ret)
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return ret;
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#endif
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} else {
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#ifdef CONFIG_X86
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bios_set_interrupt_handler(0x15, int15_handler);
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bios_run_on_x86(dev, (unsigned long)ram, vesa_mode,
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&mode_info);
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#endif
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}
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debug("Final vesa mode %#x\n", mode_info.video_mode);
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return 0;
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}
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