upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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530 lines
13 KiB
530 lines
13 KiB
/*
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* Copyright 2014-2015 Freescale Semiconductor, Inc.
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* Layerscape PCIe driver
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/fsl_serdes.h>
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#include <pci.h>
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#include <asm/io.h>
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#include <errno.h>
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#include <malloc.h>
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#ifndef CONFIG_SYS_PCI_MEMORY_BUS
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#define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE
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#endif
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#ifndef CONFIG_SYS_PCI_MEMORY_PHYS
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#define CONFIG_SYS_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE
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#endif
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#ifndef CONFIG_SYS_PCI_MEMORY_SIZE
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#define CONFIG_SYS_PCI_MEMORY_SIZE (2 * 1024 * 1024 * 1024UL) /* 2G */
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#endif
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/* iATU registers */
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#define PCIE_ATU_VIEWPORT 0x900
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#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
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#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
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#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
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#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
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#define PCIE_ATU_REGION_INDEX2 (0x2 << 0)
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#define PCIE_ATU_REGION_INDEX3 (0x3 << 0)
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#define PCIE_ATU_CR1 0x904
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#define PCIE_ATU_TYPE_MEM (0x0 << 0)
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#define PCIE_ATU_TYPE_IO (0x2 << 0)
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#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
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#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
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#define PCIE_ATU_CR2 0x908
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#define PCIE_ATU_ENABLE (0x1 << 31)
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#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
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#define PCIE_ATU_LOWER_BASE 0x90C
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#define PCIE_ATU_UPPER_BASE 0x910
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#define PCIE_ATU_LIMIT 0x914
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#define PCIE_ATU_LOWER_TARGET 0x918
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#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
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#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
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#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
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#define PCIE_ATU_UPPER_TARGET 0x91C
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/* LUT registers */
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#define PCIE_LUT_BASE 0x80000
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#define PCIE_LUT_DBG 0x7FC
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#define PCIE_DBI_RO_WR_EN 0x8bc
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#define PCIE_LINK_CAP 0x7c
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#define PCIE_LINK_SPEED_MASK 0xf
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#define PCIE_LINK_STA 0x82
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#define LTSSM_STATE_MASK 0x3f
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#define LTSSM_PCIE_L0 0x11 /* L0 state */
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#define PCIE_DBI_SIZE 0x100000 /* 1M */
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struct ls_pcie {
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int idx;
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void __iomem *dbi;
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void __iomem *va_cfg0;
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void __iomem *va_cfg1;
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struct pci_controller hose;
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};
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struct ls_pcie_info {
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unsigned long regs;
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int pci_num;
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u64 cfg0_phys;
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u64 cfg0_size;
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u64 cfg1_phys;
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u64 cfg1_size;
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u64 mem_bus;
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u64 mem_phys;
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u64 mem_size;
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u64 io_bus;
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u64 io_phys;
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u64 io_size;
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};
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#define SET_LS_PCIE_INFO(x, num) \
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{ \
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x.regs = CONFIG_SYS_PCIE##num##_ADDR; \
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x.cfg0_phys = CONFIG_SYS_PCIE_CFG0_PHYS_OFF + \
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CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
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x.cfg0_size = CONFIG_SYS_PCIE_CFG0_SIZE; \
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x.cfg1_phys = CONFIG_SYS_PCIE_CFG1_PHYS_OFF + \
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CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
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x.cfg1_size = CONFIG_SYS_PCIE_CFG1_SIZE; \
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x.mem_bus = CONFIG_SYS_PCIE_MEM_BUS; \
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x.mem_phys = CONFIG_SYS_PCIE_MEM_PHYS_OFF + \
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CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
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x.mem_size = CONFIG_SYS_PCIE_MEM_SIZE; \
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x.io_bus = CONFIG_SYS_PCIE_IO_BUS; \
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x.io_phys = CONFIG_SYS_PCIE_IO_PHYS_OFF + \
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CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
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x.io_size = CONFIG_SYS_PCIE_IO_SIZE; \
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x.pci_num = num; \
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}
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#ifdef CONFIG_LS102XA
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#include <asm/arch/immap_ls102xa.h>
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/* PEX1/2 Misc Ports Status Register */
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#define LTSSM_STATE_SHIFT 20
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static int ls_pcie_link_state(struct ls_pcie *pcie)
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{
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u32 state;
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struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
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state = in_be32(&scfg->pexmscportsr[pcie->idx]);
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state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
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if (state < LTSSM_PCIE_L0) {
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debug("....PCIe link error. LTSSM=0x%02x.\n", state);
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return 0;
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}
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return 1;
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}
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#else
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static int ls_pcie_link_state(struct ls_pcie *pcie)
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{
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u32 state;
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state = readl(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) &
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LTSSM_STATE_MASK;
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if (state < LTSSM_PCIE_L0) {
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debug("....PCIe link error. LTSSM=0x%02x.\n", state);
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return 0;
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}
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return 1;
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}
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#endif
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static int ls_pcie_link_up(struct ls_pcie *pcie)
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{
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int state;
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u32 cap;
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state = ls_pcie_link_state(pcie);
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if (state)
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return state;
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/* Try to download speed to gen1 */
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cap = readl(pcie->dbi + PCIE_LINK_CAP);
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writel((cap & (~PCIE_LINK_SPEED_MASK)) | 1, pcie->dbi + PCIE_LINK_CAP);
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/*
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* Notice: the following delay has critical impact on link training
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* if too short (<30ms) the link doesn't get up.
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*/
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mdelay(100);
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state = ls_pcie_link_state(pcie);
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if (state)
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return state;
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writel(cap, pcie->dbi + PCIE_LINK_CAP);
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return 0;
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}
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static void ls_pcie_cfg0_set_busdev(struct ls_pcie *pcie, u32 busdev)
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{
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writel(PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
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pcie->dbi + PCIE_ATU_VIEWPORT);
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writel(busdev, pcie->dbi + PCIE_ATU_LOWER_TARGET);
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}
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static void ls_pcie_cfg1_set_busdev(struct ls_pcie *pcie, u32 busdev)
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{
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writel(PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
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pcie->dbi + PCIE_ATU_VIEWPORT);
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writel(busdev, pcie->dbi + PCIE_ATU_LOWER_TARGET);
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}
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static void ls_pcie_iatu_outbound_set(struct ls_pcie *pcie, int idx, int type,
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u64 phys, u64 bus_addr, pci_size_t size)
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{
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writel(PCIE_ATU_REGION_OUTBOUND | idx, pcie->dbi + PCIE_ATU_VIEWPORT);
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writel((u32)phys, pcie->dbi + PCIE_ATU_LOWER_BASE);
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writel(phys >> 32, pcie->dbi + PCIE_ATU_UPPER_BASE);
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writel(phys + size - 1, pcie->dbi + PCIE_ATU_LIMIT);
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writel((u32)bus_addr, pcie->dbi + PCIE_ATU_LOWER_TARGET);
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writel(bus_addr >> 32, pcie->dbi + PCIE_ATU_UPPER_TARGET);
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writel(type, pcie->dbi + PCIE_ATU_CR1);
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writel(PCIE_ATU_ENABLE, pcie->dbi + PCIE_ATU_CR2);
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}
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static void ls_pcie_setup_atu(struct ls_pcie *pcie, struct ls_pcie_info *info)
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{
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#ifdef DEBUG
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int i;
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#endif
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/* ATU 0 : OUTBOUND : CFG0 */
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ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0,
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PCIE_ATU_TYPE_CFG0,
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info->cfg0_phys,
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0,
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info->cfg0_size);
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/* ATU 1 : OUTBOUND : CFG1 */
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ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX1,
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PCIE_ATU_TYPE_CFG1,
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info->cfg1_phys,
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0,
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info->cfg1_size);
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/* ATU 2 : OUTBOUND : MEM */
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ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX2,
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PCIE_ATU_TYPE_MEM,
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info->mem_phys,
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info->mem_bus,
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info->mem_size);
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/* ATU 3 : OUTBOUND : IO */
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ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX3,
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PCIE_ATU_TYPE_IO,
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info->io_phys,
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info->io_bus,
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info->io_size);
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#ifdef DEBUG
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for (i = 0; i <= PCIE_ATU_REGION_INDEX3; i++) {
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writel(PCIE_ATU_REGION_OUTBOUND | i,
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pcie->dbi + PCIE_ATU_VIEWPORT);
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debug("iATU%d:\n", i);
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debug("\tLOWER PHYS 0x%08x\n",
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readl(pcie->dbi + PCIE_ATU_LOWER_BASE));
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debug("\tUPPER PHYS 0x%08x\n",
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readl(pcie->dbi + PCIE_ATU_UPPER_BASE));
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debug("\tLOWER BUS 0x%08x\n",
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readl(pcie->dbi + PCIE_ATU_LOWER_TARGET));
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debug("\tUPPER BUS 0x%08x\n",
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readl(pcie->dbi + PCIE_ATU_UPPER_TARGET));
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debug("\tLIMIT 0x%08x\n",
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readl(pcie->dbi + PCIE_ATU_LIMIT));
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debug("\tCR1 0x%08x\n",
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readl(pcie->dbi + PCIE_ATU_CR1));
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debug("\tCR2 0x%08x\n",
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readl(pcie->dbi + PCIE_ATU_CR2));
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}
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#endif
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}
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int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
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{
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/* Do not skip controller */
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return 0;
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}
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static int ls_pcie_addr_valid(struct pci_controller *hose, pci_dev_t d)
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{
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if (PCI_DEV(d) > 0)
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return -EINVAL;
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/* Controller does not support multi-function in RC mode */
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if ((PCI_BUS(d) == hose->first_busno) && (PCI_FUNC(d) > 0))
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return -EINVAL;
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return 0;
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}
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static int ls_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
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int where, u32 *val)
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{
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struct ls_pcie *pcie = hose->priv_data;
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u32 busdev, *addr;
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if (ls_pcie_addr_valid(hose, d)) {
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*val = 0xffffffff;
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return -EINVAL;
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}
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if (PCI_BUS(d) == hose->first_busno) {
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addr = pcie->dbi + (where & ~0x3);
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} else {
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busdev = PCIE_ATU_BUS(PCI_BUS(d)) |
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PCIE_ATU_DEV(PCI_DEV(d)) |
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PCIE_ATU_FUNC(PCI_FUNC(d));
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if (PCI_BUS(d) == hose->first_busno + 1) {
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ls_pcie_cfg0_set_busdev(pcie, busdev);
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addr = pcie->va_cfg0 + (where & ~0x3);
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} else {
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ls_pcie_cfg1_set_busdev(pcie, busdev);
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addr = pcie->va_cfg1 + (where & ~0x3);
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}
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}
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*val = readl(addr);
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return 0;
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}
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static int ls_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
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int where, u32 val)
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{
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struct ls_pcie *pcie = hose->priv_data;
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u32 busdev, *addr;
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if (ls_pcie_addr_valid(hose, d))
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return -EINVAL;
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if (PCI_BUS(d) == hose->first_busno) {
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addr = pcie->dbi + (where & ~0x3);
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} else {
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busdev = PCIE_ATU_BUS(PCI_BUS(d)) |
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PCIE_ATU_DEV(PCI_DEV(d)) |
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PCIE_ATU_FUNC(PCI_FUNC(d));
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if (PCI_BUS(d) == hose->first_busno + 1) {
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ls_pcie_cfg0_set_busdev(pcie, busdev);
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addr = pcie->va_cfg0 + (where & ~0x3);
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} else {
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ls_pcie_cfg1_set_busdev(pcie, busdev);
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addr = pcie->va_cfg1 + (where & ~0x3);
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}
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}
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writel(val, addr);
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return 0;
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}
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static void ls_pcie_setup_ctrl(struct ls_pcie *pcie,
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struct ls_pcie_info *info)
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{
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struct pci_controller *hose = &pcie->hose;
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pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
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ls_pcie_setup_atu(pcie, info);
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pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0);
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/* program correct class for RC */
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writel(1, pcie->dbi + PCIE_DBI_RO_WR_EN);
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pci_hose_write_config_word(hose, dev, PCI_CLASS_DEVICE,
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PCI_CLASS_BRIDGE_PCI);
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#ifndef CONFIG_LS102XA
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writel(0, pcie->dbi + PCIE_DBI_RO_WR_EN);
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#endif
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}
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int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info *info)
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{
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struct ls_pcie *pcie;
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struct pci_controller *hose;
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int num = dev - PCIE1;
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pci_dev_t pdev = PCI_BDF(busno, 0, 0);
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int i, linkup, ep_mode;
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u8 header_type;
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u16 temp16;
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if (!is_serdes_configured(dev)) {
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printf("PCIe%d: disabled\n", num + 1);
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return busno;
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}
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pcie = malloc(sizeof(*pcie));
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if (!pcie)
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return busno;
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memset(pcie, 0, sizeof(*pcie));
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hose = &pcie->hose;
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hose->priv_data = pcie;
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hose->first_busno = busno;
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pcie->idx = num;
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pcie->dbi = map_physmem(info->regs, PCIE_DBI_SIZE, MAP_NOCACHE);
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pcie->va_cfg0 = map_physmem(info->cfg0_phys,
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info->cfg0_size,
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MAP_NOCACHE);
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pcie->va_cfg1 = map_physmem(info->cfg1_phys,
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info->cfg1_size,
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MAP_NOCACHE);
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/* outbound memory */
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pci_set_region(&hose->regions[0],
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(pci_size_t)info->mem_bus,
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(phys_size_t)info->mem_phys,
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(pci_size_t)info->mem_size,
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PCI_REGION_MEM);
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/* outbound io */
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pci_set_region(&hose->regions[1],
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(pci_size_t)info->io_bus,
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(phys_size_t)info->io_phys,
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(pci_size_t)info->io_size,
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PCI_REGION_IO);
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/* System memory space */
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pci_set_region(&hose->regions[2],
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CONFIG_SYS_PCI_MEMORY_BUS,
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CONFIG_SYS_PCI_MEMORY_PHYS,
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CONFIG_SYS_PCI_MEMORY_SIZE,
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PCI_REGION_SYS_MEMORY);
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hose->region_count = 3;
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for (i = 0; i < hose->region_count; i++)
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debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n",
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i,
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(u64)hose->regions[i].phys_start,
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(u64)hose->regions[i].bus_start,
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(u64)hose->regions[i].size,
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hose->regions[i].flags);
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pci_set_ops(hose,
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pci_hose_read_config_byte_via_dword,
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pci_hose_read_config_word_via_dword,
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ls_pcie_read_config,
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pci_hose_write_config_byte_via_dword,
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pci_hose_write_config_word_via_dword,
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ls_pcie_write_config);
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pci_hose_read_config_byte(hose, pdev, PCI_HEADER_TYPE, &header_type);
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ep_mode = (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
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printf("PCIe%u: %s ", info->pci_num,
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ep_mode ? "Endpoint" : "Root Complex");
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linkup = ls_pcie_link_up(pcie);
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if (!linkup) {
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/* Let the user know there's no PCIe link */
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printf("no link, regs @ 0x%lx\n", info->regs);
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hose->last_busno = hose->first_busno;
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return busno;
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}
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/* Print the negotiated PCIe link width */
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pci_hose_read_config_word(hose, pdev, PCIE_LINK_STA, &temp16);
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printf("x%d gen%d, regs @ 0x%lx\n", (temp16 & 0x3f0) >> 4,
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(temp16 & 0xf), info->regs);
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if (ep_mode)
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return busno;
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ls_pcie_setup_ctrl(pcie, info);
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pci_register_hose(hose);
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hose->last_busno = pci_hose_scan(hose);
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|
|
|
printf("PCIe%x: Bus %02x - %02x\n",
|
|
info->pci_num, hose->first_busno, hose->last_busno);
|
|
|
|
return hose->last_busno + 1;
|
|
}
|
|
|
|
int ls_pcie_init_board(int busno)
|
|
{
|
|
struct ls_pcie_info info;
|
|
|
|
#ifdef CONFIG_PCIE1
|
|
SET_LS_PCIE_INFO(info, 1);
|
|
busno = ls_pcie_init_ctrl(busno, PCIE1, &info);
|
|
#endif
|
|
|
|
#ifdef CONFIG_PCIE2
|
|
SET_LS_PCIE_INFO(info, 2);
|
|
busno = ls_pcie_init_ctrl(busno, PCIE2, &info);
|
|
#endif
|
|
|
|
#ifdef CONFIG_PCIE3
|
|
SET_LS_PCIE_INFO(info, 3);
|
|
busno = ls_pcie_init_ctrl(busno, PCIE3, &info);
|
|
#endif
|
|
|
|
#ifdef CONFIG_PCIE4
|
|
SET_LS_PCIE_INFO(info, 4);
|
|
busno = ls_pcie_init_ctrl(busno, PCIE4, &info);
|
|
#endif
|
|
|
|
return busno;
|
|
}
|
|
|
|
void pci_init_board(void)
|
|
{
|
|
ls_pcie_init_board(0);
|
|
}
|
|
|
|
#ifdef CONFIG_OF_BOARD_SETUP
|
|
#include <libfdt.h>
|
|
#include <fdt_support.h>
|
|
|
|
static void ft_pcie_ls_setup(void *blob, const char *pci_compat,
|
|
unsigned long ctrl_addr, enum srds_prtcl dev)
|
|
{
|
|
int off;
|
|
|
|
off = fdt_node_offset_by_compat_reg(blob, pci_compat,
|
|
(phys_addr_t)ctrl_addr);
|
|
if (off < 0)
|
|
return;
|
|
|
|
if (!is_serdes_configured(dev))
|
|
fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
|
|
}
|
|
|
|
void ft_pci_setup(void *blob, bd_t *bd)
|
|
{
|
|
#ifdef CONFIG_PCIE1
|
|
ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE1_ADDR, PCIE1);
|
|
#endif
|
|
|
|
#ifdef CONFIG_PCIE2
|
|
ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE2_ADDR, PCIE2);
|
|
#endif
|
|
|
|
#ifdef CONFIG_PCIE3
|
|
ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE3_ADDR, PCIE3);
|
|
#endif
|
|
|
|
#ifdef CONFIG_PCIE4
|
|
ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE4_ADDR, PCIE4);
|
|
#endif
|
|
}
|
|
|
|
#else
|
|
void ft_pci_setup(void *blob, bd_t *bd)
|
|
{
|
|
}
|
|
#endif
|
|
|