upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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94 lines
3.3 KiB
94 lines
3.3 KiB
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Based on Linux i.MX iomux-v3.h file:
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* Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
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* <armlinux@phytec.de>
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*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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*/
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#ifndef __MACH_IOMUX_H__
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#define __MACH_IOMUX_H__
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/*
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* build IOMUX_PAD structure
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*
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* This iomux scheme is based around pads, which are the physical balls
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* on the processor.
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*
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* - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls
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* things like driving strength and pullup/pulldown.
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* - Each pad can have but not necessarily does have an output routing register
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* (IOMUXC_SW_MUX_CTL_PAD_x).
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* - Each pad can have but not necessarily does have an input routing register
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* (IOMUXC_x_SELECT_INPUT)
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*
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* The three register sets do not have a fixed offset to each other,
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* hence we order this table by pad control registers (which all pads
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* have) and put the optional i/o routing registers into additional
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* fields.
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*
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* The naming convention for the pad modes is SOC_PAD_<padname>__<padmode>
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* If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
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*
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* IOMUX/PAD Bit field definitions
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*
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* MUX_CTRL_OFS: 0..15 (16)
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* SEL_INPUT_OFS: 16..31 (16)
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* MUX_MODE: 32..37 (6)
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* SEL_INP: 38..41 (4)
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* PAD_CTRL + NO_PAD_CTRL: 42..60 (19)
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* reserved: 61-63 (3)
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*/
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typedef u64 iomux_cfg_t;
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#define MUX_CTRL_OFS_SHIFT 0
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#define MUX_CTRL_OFS_MASK ((iomux_cfg_t)0xffff << MUX_CTRL_OFS_SHIFT)
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#define MUX_SEL_INPUT_OFS_SHIFT 16
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#define MUX_SEL_INPUT_OFS_MASK ((iomux_cfg_t)0xffff << \
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MUX_SEL_INPUT_OFS_SHIFT)
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#define MUX_MODE_SHIFT 32
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#define MUX_MODE_MASK ((iomux_cfg_t)0x3f << MUX_MODE_SHIFT)
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#define MUX_SEL_INPUT_SHIFT 38
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#define MUX_SEL_INPUT_MASK ((iomux_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
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#define MUX_PAD_CTRL_SHIFT 42
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#define MUX_PAD_CTRL_MASK ((iomux_cfg_t)0x7ffff << MUX_PAD_CTRL_SHIFT)
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#define MUX_PAD_CTRL(x) ((iomux_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
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#define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \
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sel_input, pad_ctrl) \
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(((iomux_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \
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((iomux_cfg_t)(mux_mode) << MUX_MODE_SHIFT) | \
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((iomux_cfg_t)(pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \
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((iomux_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)| \
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((iomux_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT))
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#define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | \
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MUX_PAD_CTRL(pad))
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#define IOMUX_CONFIG_MPORTS 0x20
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#define MUX_MODE_MPORTS ((iomux_v3_cfg_t)IOMUX_CONFIG_MPORTS << \
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MUX_MODE_SHIFT)
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/* Bit definition below needs to be fixed acccording to ulp rm */
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#define NO_PAD_CTRL (1 << 18)
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#define PAD_CTL_OBE_ENABLE (1 << 17)
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#define PAD_CTL_IBE_ENABLE (1 << 16)
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#define PAD_CTL_DSE (1 << 6)
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#define PAD_CTL_ODE (1 << 5)
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#define PAD_CTL_SRE_FAST (0 << 2)
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#define PAD_CTL_SRE_SLOW (1 << 2)
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#define PAD_CTL_PUE (1 << 1)
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#define PAD_CTL_PUS_UP ((1 << 0) | PAD_CTL_PUE)
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#define PAD_CTL_PUS_DOWN ((0 << 0) | PAD_CTL_PUE)
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void mx7ulp_iomux_setup_pad(iomux_cfg_t pad);
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void mx7ulp_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list,
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unsigned count);
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#endif /* __MACH_IOMUX_H__*/
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