upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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341 lines
12 KiB
341 lines
12 KiB
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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*/
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#ifndef _ASM_ARCH_SCG_H
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#define _ASM_ARCH_SCG_H
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#include <common.h>
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#ifdef CONFIG_CLK_DEBUG
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#define clk_debug(fmt, args...) printf(fmt, ##args)
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#else
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#define clk_debug(fmt, args...)
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#endif
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#define SCG_CCR_SCS_SHIFT (24)
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#define SCG_CCR_SCS_MASK ((0xFUL) << SCG_CCR_SCS_SHIFT)
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#define SCG_CCR_DIVCORE_SHIFT (16)
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#define SCG_CCR_DIVCORE_MASK ((0xFUL) << SCG_CCR_DIVCORE_SHIFT)
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#define SCG_CCR_DIVPLAT_SHIFT (12)
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#define SCG_CCR_DIVPLAT_MASK ((0xFUL) << SCG_CCR_DIVPLAT_SHIFT)
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#define SCG_CCR_DIVEXT_SHIFT (8)
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#define SCG_CCR_DIVEXT_MASK ((0xFUL) << SCG_CCR_DIVEXT_SHIFT)
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#define SCG_CCR_DIVBUS_SHIFT (4)
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#define SCG_CCR_DIVBUS_MASK ((0xFUL) << SCG_CCR_DIVBUS_SHIFT)
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#define SCG_CCR_DIVSLOW_SHIFT (0)
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#define SCG_CCR_DIVSLOW_MASK ((0xFUL) << SCG_CCR_DIVSLOW_SHIFT)
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/* SCG DDR Clock Control Register */
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#define SCG_DDRCCR_DDRCS_SHIFT (24)
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#define SCG_DDRCCR_DDRCS_MASK ((0x1UL) << SCG_DDRCCR_DDRCS_SHIFT)
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#define SCG_DDRCCR_DDRDIV_SHIFT (0)
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#define SCG_DDRCCR_DDRDIV_MASK ((0x7UL) << SCG_DDRCCR_DDRDIV_SHIFT)
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/* SCG NIC Clock Control Register */
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#define SCG_NICCCR_NICCS_SHIFT (28)
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#define SCG_NICCCR_NICCS_MASK ((0x1UL) << SCG_NICCCR_NICCS_SHIFT)
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#define SCG_NICCCR_NIC0_DIV_SHIFT (24)
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#define SCG_NICCCR_NIC0_DIV_MASK ((0xFUL) << SCG_NICCCR_NIC0_DIV_SHIFT)
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#define SCG_NICCCR_GPU_DIV_SHIFT (20)
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#define SCG_NICCCR_GPU_DIV_MASK ((0xFUL) << SCG_NICCCR_GPU_DIV_SHIFT)
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#define SCG_NICCCR_NIC1_DIV_SHIFT (16)
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#define SCG_NICCCR_NIC1_DIV_MASK ((0xFUL) << SCG_NICCCR_NIC1_DIV_SHIFT)
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#define SCG_NICCCR_NIC1_DIVEXT_SHIFT (8)
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#define SCG_NICCCR_NIC1_DIVEXT_MASK ((0xFUL) << SCG_NICCCR_NIC1_DIVEXT_SHIFT)
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#define SCG_NICCCR_NIC1_DIVBUS_SHIFT (4)
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#define SCG_NICCCR_NIC1_DIVBUS_MASK ((0xFUL) << SCG_NICCCR_NIC1_DIVBUS_SHIFT)
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/* SCG NIC clock status register */
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#define SCG_NICCSR_NICCS_SHIFT (28)
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#define SCG_NICCSR_NICCS_MASK ((0x1UL) << SCG_NICCSR_NICCS_SHIFT)
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#define SCG_NICCSR_NIC0DIV_SHIFT (24)
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#define SCG_NICCSR_NIC0DIV_MASK ((0xFUL) << SCG_NICCSR_NIC0DIV_SHIFT)
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#define SCG_NICCSR_GPUDIV_SHIFT (20)
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#define SCG_NICCSR_GPUDIV_MASK ((0xFUL) << SCG_NICCSR_GPUDIV_SHIFT)
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#define SCG_NICCSR_NIC1DIV_SHIFT (16)
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#define SCG_NICCSR_NIC1DIV_MASK ((0xFUL) << SCG_NICCSR_NIC1DIV_SHIFT)
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#define SCG_NICCSR_NIC1EXTDIV_SHIFT (8)
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#define SCG_NICCSR_NIC1EXTDIV_MASK ((0xFUL) << SCG_NICCSR_NIC1EXTDIV_SHIFT)
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#define SCG_NICCSR_NIC1BUSDIV_SHIFT (4)
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#define SCG_NICCSR_NIC1BUSDIV_MASK ((0xFUL) << SCG_NICCSR_NIC1BUSDIV_SHIFT)
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/* SCG Slow IRC Control Status Register */
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#define SCG_SIRC_CSR_SIRCVLD_SHIFT (24)
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#define SCG_SIRC_CSR_SIRCVLD_MASK ((0x1UL) << SCG_SIRC_CSR_SIRCVLD_SHIFT)
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#define SCG_SIRC_CSR_SIRCEN_SHIFT (0)
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#define SCG_SIRC_CSR_SIRCEN_MASK ((0x1UL) << SCG_SIRC_CSR_SIRCEN_SHIFT)
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/* SCG Slow IRC Configuration Register */
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#define SCG_SIRCCFG_RANGE_SHIFT (0)
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#define SCG_SIRCCFG_RANGE_MASK ((0x1UL) << SCG_SIRCCFG_RANGE_SHIFT)
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#define SCG_SIRCCFG_RANGE_4M ((0x0UL) << SCG_SIRCCFG_RANGE_SHIFT)
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#define SCG_SIRCCFG_RANGE_16M ((0x1UL) << SCG_SIRCCFG_RANGE_SHIFT)
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/* SCG Slow IRC Divide Register */
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#define SCG_SIRCDIV_DIV3_SHIFT (16)
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#define SCG_SIRCDIV_DIV3_MASK ((0x7UL) << SCG_SIRCDIV_DIV3_SHIFT)
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#define SCG_SIRCDIV_DIV2_SHIFT (8)
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#define SCG_SIRCDIV_DIV2_MASK ((0x7UL) << SCG_SIRCDIV_DIV2_SHIFT)
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#define SCG_SIRCDIV_DIV1_SHIFT (0)
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#define SCG_SIRCDIV_DIV1_MASK ((0x7UL) << SCG_SIRCDIV_DIV1_SHIFT)
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/*
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* FIRC/SIRC DIV1 ==> xIRC_PLAT_CLK
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* FIRC/SIRC DIV2 ==> xIRC_BUS_CLK
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* FIRC/SIRC DIV3 ==> xIRC_SLOW_CLK
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*/
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/* SCG Fast IRC Control Status Register */
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#define SCG_FIRC_CSR_FIRCVLD_SHIFT (24)
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#define SCG_FIRC_CSR_FIRCVLD_MASK ((0x1UL) << SCG_FIRC_CSR_FIRCVLD_SHIFT)
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#define SCG_FIRC_CSR_FIRCEN_SHIFT (0)
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#define SCG_FIRC_CSR_FIRCEN_MASK ((0x1UL) << SCG_FIRC_CSR_FIRCEN_SHIFT)
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/* SCG Fast IRC Divide Register */
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#define SCG_FIRCDIV_DIV3_SHIFT (16)
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#define SCG_FIRCDIV_DIV3_MASK ((0x7UL) << SCG_FIRCDIV_DIV3_SHIFT)
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#define SCG_FIRCDIV_DIV2_SHIFT (8)
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#define SCG_FIRCDIV_DIV2_MASK ((0x7UL) << SCG_FIRCDIV_DIV2_SHIFT)
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#define SCG_FIRCDIV_DIV1_SHIFT (0)
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#define SCG_FIRCDIV_DIV1_MASK ((0x7UL) << SCG_FIRCDIV_DIV1_SHIFT)
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#define SCG_FIRCCFG_RANGE_SHIFT (0)
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#define SCG_FIRCCFG_RANGE_MASK ((0x3UL) << SCG_FIRCCFG_RANGE_SHIFT)
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#define SCG_FIRCCFG_RANGE_SHIFT (0)
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#define SCG_FIRCCFG_RANGE_48M ((0x0UL) << SCG_FIRCCFG_RANGE_SHIFT)
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/* SCG System OSC Control Status Register */
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#define SCG_SOSC_CSR_SOSCVLD_SHIFT (24)
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#define SCG_SOSC_CSR_SOSCVLD_MASK ((0x1UL) << SCG_SOSC_CSR_SOSCVLD_SHIFT)
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/* SCG Fast IRC Divide Register */
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#define SCG_SOSCDIV_DIV3_SHIFT (16)
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#define SCG_SOSCDIV_DIV3_MASK ((0x7UL) << SCG_SOSCDIV_DIV3_SHIFT)
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#define SCG_SOSCDIV_DIV2_SHIFT (8)
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#define SCG_SOSCDIV_DIV2_MASK ((0x7UL) << SCG_SOSCDIV_DIV2_SHIFT)
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#define SCG_SOSCDIV_DIV1_SHIFT (0)
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#define SCG_SOSCDIV_DIV1_MASK ((0x7UL) << SCG_SOSCDIV_DIV1_SHIFT)
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/* SCG RTC OSC Control Status Register */
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#define SCG_ROSC_CSR_ROSCVLD_SHIFT (24)
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#define SCG_ROSC_CSR_ROSCVLD_MASK ((0x1UL) << SCG_ROSC_CSR_ROSCVLD_SHIFT)
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#define SCG_SPLL_CSR_SPLLVLD_SHIFT (24)
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#define SCG_SPLL_CSR_SPLLVLD_MASK ((0x1UL) << SCG_SPLL_CSR_SPLLVLD_SHIFT)
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#define SCG_SPLL_CSR_SPLLEN_SHIFT (0)
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#define SCG_SPLL_CSR_SPLLEN_MASK ((0x1UL) << SCG_SPLL_CSR_SPLLEN_SHIFT)
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#define SCG_APLL_CSR_APLLEN_SHIFT (0)
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#define SCG_APLL_CSR_APLLEN_MASK (0x1UL)
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#define SCG_APLL_CSR_APLLVLD_MASK (0x01000000)
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#define SCG_UPLL_CSR_UPLLVLD_MASK (0x01000000)
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#define SCG_PLL_PFD3_GATE_MASK (0x80000000)
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#define SCG_PLL_PFD2_GATE_MASK (0x00800000)
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#define SCG_PLL_PFD1_GATE_MASK (0x00008000)
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#define SCG_PLL_PFD0_GATE_MASK (0x00000080)
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#define SCG_PLL_PFD3_VALID_MASK (0x40000000)
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#define SCG_PLL_PFD2_VALID_MASK (0x00400000)
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#define SCG_PLL_PFD1_VALID_MASK (0x00004000)
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#define SCG_PLL_PFD0_VALID_MASK (0x00000040)
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#define SCG_PLL_PFD0_FRAC_SHIFT (0)
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#define SCG_PLL_PFD0_FRAC_MASK ((0x3F) << SCG_PLL_PFD0_FRAC_SHIFT)
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#define SCG_PLL_PFD1_FRAC_SHIFT (8)
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#define SCG_PLL_PFD1_FRAC_MASK ((0x3F) << SCG_PLL_PFD1_FRAC_SHIFT)
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#define SCG_PLL_PFD2_FRAC_SHIFT (16)
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#define SCG_PLL_PFD2_FRAC_MASK ((0x3F) << SCG_PLL_PFD2_FRAC_SHIFT)
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#define SCG_PLL_PFD3_FRAC_SHIFT (24)
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#define SCG_PLL_PFD3_FRAC_MASK ((0x3F) << SCG_PLL_PFD3_FRAC_SHIFT)
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#define SCG_PLL_CFG_POSTDIV2_SHIFT (28)
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#define SCG_PLL_CFG_POSTDIV2_MASK ((0xFUL) << SCG_PLL_CFG_POSTDIV2_SHIFT)
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#define SCG_PLL_CFG_POSTDIV1_SHIFT (24)
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#define SCG_PLL_CFG_POSTDIV1_MASK ((0xFUL) << SCG_PLL_CFG_POSTDIV1_SHIFT)
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#define SCG_PLL_CFG_MULT_SHIFT (16)
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#define SCG1_SPLL_CFG_MULT_MASK ((0x7FUL) << SCG_PLL_CFG_MULT_SHIFT)
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#define SCG_APLL_CFG_MULT_MASK ((0x7FUL) << SCG_PLL_CFG_MULT_SHIFT)
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#define SCG_PLL_CFG_PFDSEL_SHIFT (14)
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#define SCG_PLL_CFG_PFDSEL_MASK ((0x3UL) << SCG_PLL_CFG_PFDSEL_SHIFT)
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#define SCG_PLL_CFG_PREDIV_SHIFT (8)
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#define SCG_PLL_CFG_PREDIV_MASK ((0x7UL) << SCG_PLL_CFG_PREDIV_SHIFT)
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#define SCG_PLL_CFG_BYPASS_SHIFT (2)
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/* 0: SPLL, 1: bypass */
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#define SCG_PLL_CFG_BYPASS_MASK ((0x1UL) << SCG_PLL_CFG_BYPASS_SHIFT)
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#define SCG_PLL_CFG_PLLSEL_SHIFT (1)
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/* 0: pll, 1: pfd */
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#define SCG_PLL_CFG_PLLSEL_MASK ((0x1UL) << SCG_PLL_CFG_PLLSEL_SHIFT)
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#define SCG_PLL_CFG_CLKSRC_SHIFT (0)
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/* 0: Sys-OSC, 1: FIRC */
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#define SCG_PLL_CFG_CLKSRC_MASK ((0x1UL) << SCG_PLL_CFG_CLKSRC_SHIFT)
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#define SCG0_SPLL_CFG_MULT_SHIFT (17)
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/* 0: Multiplier = 20, 1: Multiplier = 22 */
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#define SCG0_SPLL_CFG_MULT_MASK ((0x1UL) << SCG0_SPLL_CFG_MULT_SHIFT)
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#define PLL_USB_EN_USB_CLKS_MASK (0x01 << 6)
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#define PLL_USB_PWR_MASK (0x01 << 12)
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#define PLL_USB_ENABLE_MASK (0x01 << 13)
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#define PLL_USB_BYPASS_MASK (0x01 << 16)
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#define PLL_USB_REG_ENABLE_MASK (0x01 << 21)
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#define PLL_USB_DIV_SEL_MASK (0x07 << 22)
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#define PLL_USB_LOCK_MASK (0x01 << 31)
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enum scg_clk {
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SCG_SOSC_CLK,
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SCG_FIRC_CLK,
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SCG_SIRC_CLK,
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SCG_ROSC_CLK,
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SCG_SIRC_DIV1_CLK,
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SCG_SIRC_DIV2_CLK,
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SCG_SIRC_DIV3_CLK,
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SCG_FIRC_DIV1_CLK,
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SCG_FIRC_DIV2_CLK,
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SCG_FIRC_DIV3_CLK,
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SCG_SOSC_DIV1_CLK,
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SCG_SOSC_DIV2_CLK,
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SCG_SOSC_DIV3_CLK,
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SCG_CORE_CLK,
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SCG_BUS_CLK,
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SCG_SPLL_PFD0_CLK,
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SCG_SPLL_PFD1_CLK,
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SCG_SPLL_PFD2_CLK,
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SCG_SPLL_PFD3_CLK,
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SCG_DDR_CLK,
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SCG_NIC0_CLK,
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SCG_GPU_CLK,
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SCG_NIC1_CLK,
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SCG_NIC1_BUS_CLK,
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SCG_NIC1_EXT_CLK,
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SCG_APLL_PFD0_CLK,
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SCG_APLL_PFD1_CLK,
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SCG_APLL_PFD2_CLK,
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SCG_APLL_PFD3_CLK,
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USB_PLL_OUT,
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MIPI_PLL_OUT
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};
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enum scg_sys_src {
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SCG_SCS_SYS_OSC = 1,
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SCG_SCS_SLOW_IRC,
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SCG_SCS_FAST_IRC,
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SCG_SCS_RTC_OSC,
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SCG_SCS_AUX_PLL,
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SCG_SCS_SYS_PLL,
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SCG_SCS_USBPHY_PLL,
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};
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/* PLL supported by i.mx7ulp */
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enum pll_clocks {
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PLL_M4_SPLL, /* M4 SPLL */
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PLL_M4_APLL, /* M4 APLL*/
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PLL_A7_SPLL, /* A7 SPLL */
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PLL_A7_APLL, /* A7 APLL */
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PLL_USB, /* USB PLL*/
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PLL_MIPI, /* MIPI PLL */
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};
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typedef struct scg_regs {
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u32 verid; /* VERSION_ID */
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u32 param; /* PARAMETER */
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u32 rsvd11[2];
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u32 csr; /* Clock Status Register */
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u32 rccr; /* Run Clock Control Register */
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u32 vccr; /* VLPR Clock Control Register */
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u32 hccr; /* HSRUN Clock Control Register */
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u32 clkoutcnfg; /* SCG CLKOUT Configuration Register */
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u32 rsvd12[3];
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u32 ddrccr; /* SCG DDR Clock Control Register */
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u32 rsvd13[3];
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u32 nicccr; /* NIC Clock Control Register */
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u32 niccsr; /* NIC Clock Status Register */
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u32 rsvd10[46];
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u32 sosccsr; /* System OSC Control Status Register, offset 0x100 */
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u32 soscdiv; /* System OSC Divide Register */
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u32 sosccfg; /* System Oscillator Configuration Register */
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u32 sosctest; /* System Oscillator Test Register */
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u32 rsvd20[60];
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u32 sirccsr; /* Slow IRC Control Status Register, offset 0x200 */
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u32 sircdiv; /* Slow IRC Divide Register */
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u32 sirccfg; /* Slow IRC Configuration Register */
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u32 sirctrim; /* Slow IRC Trim Register */
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u32 loptrim; /* Low Power Oscillator Trim Register */
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u32 sirctest; /* Slow IRC Test Register */
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u32 rsvd30[58];
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u32 firccsr; /* Fast IRC Control Status Register, offset 0x300 */
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u32 fircdiv;
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u32 firccfg;
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u32 firctcfg; /* Fast IRC Trim Configuration Register */
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u32 firctriml; /* Fast IRC Trim Low Register */
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u32 firctrimh;
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u32 fircstat; /* Fast IRC Status Register */
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u32 firctest; /* Fast IRC Test Register */
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u32 rsvd40[56];
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u32 rtccsr; /* RTC OSC Control Status Register, offset 0x400 */
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u32 rsvd50[63];
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u32 apllcsr; /* Auxiliary PLL Control Status Register, offset 0x500 */
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u32 aplldiv; /* Auxiliary PLL Divider Register */
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u32 apllcfg; /* Auxiliary PLL Configuration Register */
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u32 apllpfd; /* Auxiliary PLL PFD Register */
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u32 apllnum; /* Auxiliary PLL Numerator Register */
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u32 aplldenom; /* Auxiliary PLL Denominator Register */
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u32 apllss; /* Auxiliary PLL Spread Spectrum Register */
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u32 rsvd60[55];
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u32 apllock_cnfg; /* Auxiliary PLL LOCK Configuration Register */
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u32 rsvd61[1];
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u32 spllcsr; /* System PLL Control Status Register, offset 0x600 */
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u32 splldiv; /* System PLL Divide Register */
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u32 spllcfg; /* System PLL Configuration Register */
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u32 spllpfd; /* System PLL Test Register */
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u32 spllnum; /* System PLL Numerator Register */
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u32 splldenom; /* System PLL Denominator Register */
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u32 spllss; /* System PLL Spread Spectrum Register */
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u32 rsvd70[55];
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u32 spllock_cnfg; /* System PLL LOCK Configuration Register */
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u32 rsvd71[1];
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u32 upllcsr; /* USB PLL Control Status Register, offset 0x700 */
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u32 uplldiv; /* USB PLL Divide Register */
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u32 upllcfg; /* USB PLL Configuration Register */
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} scg_t, *scg_p;
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u32 scg_clk_get_rate(enum scg_clk clk);
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int scg_enable_pll_pfd(enum scg_clk clk, u32 frac);
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int scg_enable_usb_pll(bool usb_control);
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u32 decode_pll(enum pll_clocks pll);
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void scg_a7_rccr_init(void);
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void scg_a7_spll_init(void);
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void scg_a7_ddrclk_init(void);
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void scg_a7_apll_init(void);
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void scg_a7_firc_init(void);
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void scg_a7_nicclk_init(void);
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void scg_a7_sys_clk_sel(enum scg_sys_src clk);
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void scg_a7_info(void);
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void scg_a7_soscdiv_init(void);
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#endif
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