upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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435 lines
12 KiB
435 lines
12 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) 2015 Siarhei Siamashka <siarhei.siamashka@gmail.com>
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*/
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/*
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* Support for the SSD2828 bridge chip, which can take pixel data coming
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* from a parallel LCD interface and translate it on the flight into MIPI DSI
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* interface for driving a MIPI compatible TFT display.
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*/
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#include <common.h>
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#include <mipi_display.h>
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#include <asm/arch/gpio.h>
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#include <asm/gpio.h>
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#include "videomodes.h"
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#include "ssd2828.h"
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#define SSD2828_DIR 0xB0
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#define SSD2828_VICR1 0xB1
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#define SSD2828_VICR2 0xB2
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#define SSD2828_VICR3 0xB3
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#define SSD2828_VICR4 0xB4
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#define SSD2828_VICR5 0xB5
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#define SSD2828_VICR6 0xB6
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#define SSD2828_CFGR 0xB7
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#define SSD2828_VCR 0xB8
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#define SSD2828_PCR 0xB9
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#define SSD2828_PLCR 0xBA
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#define SSD2828_CCR 0xBB
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#define SSD2828_PSCR1 0xBC
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#define SSD2828_PSCR2 0xBD
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#define SSD2828_PSCR3 0xBE
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#define SSD2828_PDR 0xBF
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#define SSD2828_OCR 0xC0
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#define SSD2828_MRSR 0xC1
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#define SSD2828_RDCR 0xC2
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#define SSD2828_ARSR 0xC3
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#define SSD2828_LCR 0xC4
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#define SSD2828_ICR 0xC5
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#define SSD2828_ISR 0xC6
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#define SSD2828_ESR 0xC7
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#define SSD2828_DAR1 0xC9
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#define SSD2828_DAR2 0xCA
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#define SSD2828_DAR3 0xCB
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#define SSD2828_DAR4 0xCC
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#define SSD2828_DAR5 0xCD
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#define SSD2828_DAR6 0xCE
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#define SSD2828_HTTR1 0xCF
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#define SSD2828_HTTR2 0xD0
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#define SSD2828_LRTR1 0xD1
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#define SSD2828_LRTR2 0xD2
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#define SSD2828_TSR 0xD3
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#define SSD2828_LRR 0xD4
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#define SSD2828_PLLR 0xD5
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#define SSD2828_TR 0xD6
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#define SSD2828_TECR 0xD7
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#define SSD2828_ACR1 0xD8
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#define SSD2828_ACR2 0xD9
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#define SSD2828_ACR3 0xDA
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#define SSD2828_ACR4 0xDB
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#define SSD2828_IOCR 0xDC
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#define SSD2828_VICR7 0xDD
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#define SSD2828_LCFR 0xDE
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#define SSD2828_DAR7 0xDF
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#define SSD2828_PUCR1 0xE0
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#define SSD2828_PUCR2 0xE1
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#define SSD2828_PUCR3 0xE2
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#define SSD2828_CBCR1 0xE9
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#define SSD2828_CBCR2 0xEA
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#define SSD2828_CBSR 0xEB
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#define SSD2828_ECR 0xEC
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#define SSD2828_VSDR 0xED
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#define SSD2828_TMR 0xEE
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#define SSD2828_GPIO1 0xEF
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#define SSD2828_GPIO2 0xF0
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#define SSD2828_DLYA01 0xF1
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#define SSD2828_DLYA23 0xF2
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#define SSD2828_DLYB01 0xF3
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#define SSD2828_DLYB23 0xF4
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#define SSD2828_DLYC01 0xF5
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#define SSD2828_DLYC23 0xF6
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#define SSD2828_ACR5 0xF7
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#define SSD2828_RR 0xFF
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#define SSD2828_CFGR_HS (1 << 0)
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#define SSD2828_CFGR_CKE (1 << 1)
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#define SSD2828_CFGR_SLP (1 << 2)
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#define SSD2828_CFGR_VEN (1 << 3)
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#define SSD2828_CFGR_HCLK (1 << 4)
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#define SSD2828_CFGR_CSS (1 << 5)
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#define SSD2828_CFGR_DCS (1 << 6)
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#define SSD2828_CFGR_REN (1 << 7)
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#define SSD2828_CFGR_ECD (1 << 8)
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#define SSD2828_CFGR_EOT (1 << 9)
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#define SSD2828_CFGR_LPE (1 << 10)
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#define SSD2828_CFGR_TXD (1 << 11)
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#define SSD2828_VIDEO_MODE_NON_BURST_WITH_SYNC_PULSES (0 << 2)
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#define SSD2828_VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (1 << 2)
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#define SSD2828_VIDEO_MODE_BURST (2 << 2)
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#define SSD2828_VIDEO_PIXEL_FORMAT_16BPP 0
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#define SSD2828_VIDEO_PIXEL_FORMAT_18BPP_PACKED 1
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#define SSD2828_VIDEO_PIXEL_FORMAT_18BPP_LOOSELY_PACKED 2
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#define SSD2828_VIDEO_PIXEL_FORMAT_24BPP 3
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#define SSD2828_LP_CLOCK_DIVIDER(n) (((n) - 1) & 0x3F)
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/*
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* SPI transfer, using the "24-bit 3 wire" mode (that's how it is called in
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* the SSD2828 documentation). The 'dout' input parameter specifies 24-bits
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* of data to be written to SSD2828. Returns the lowest 16-bits of data,
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* that is received back.
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*/
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static u32 soft_spi_xfer_24bit_3wire(const struct ssd2828_config *drv, u32 dout)
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{
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int j, bitlen = 24;
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u32 tmpdin = 0;
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/*
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* According to the "24 Bit 3 Wire SPI Interface Timing Characteristics"
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* and "TX_CLK Timing Characteristics" tables in the SSD2828 datasheet,
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* the lowest possible 'tx_clk' clock frequency is 8MHz, and SPI runs
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* at 1/8 of that after reset. So using 1 microsecond delays is safe in
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* the main loop. But the delays around chip select pin manipulations
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* need to be longer (up to 16 'tx_clk' cycles, or 2 microseconds in
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* the worst case).
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*/
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const int spi_delay_us = 1;
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const int spi_cs_delay_us = 2;
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gpio_set_value(drv->csx_pin, 0);
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udelay(spi_cs_delay_us);
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for (j = bitlen - 1; j >= 0; j--) {
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gpio_set_value(drv->sck_pin, 0);
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gpio_set_value(drv->sdi_pin, (dout & (1 << j)) != 0);
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udelay(spi_delay_us);
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if (drv->sdo_pin != -1)
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tmpdin = (tmpdin << 1) | gpio_get_value(drv->sdo_pin);
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gpio_set_value(drv->sck_pin, 1);
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udelay(spi_delay_us);
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}
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udelay(spi_cs_delay_us);
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gpio_set_value(drv->csx_pin, 1);
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udelay(spi_cs_delay_us);
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return tmpdin & 0xFFFF;
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}
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/*
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* Read from a SSD2828 hardware register (regnum >= 0xB0)
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*/
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static u32 read_hw_register(const struct ssd2828_config *cfg, u8 regnum)
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{
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soft_spi_xfer_24bit_3wire(cfg, 0x700000 | regnum);
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return soft_spi_xfer_24bit_3wire(cfg, 0x730000);
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}
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/*
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* Write to a SSD2828 hardware register (regnum >= 0xB0)
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*/
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static void write_hw_register(const struct ssd2828_config *cfg, u8 regnum,
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u16 val)
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{
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soft_spi_xfer_24bit_3wire(cfg, 0x700000 | regnum);
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soft_spi_xfer_24bit_3wire(cfg, 0x720000 | val);
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}
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/*
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* Send MIPI command to the LCD panel (cmdnum < 0xB0)
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*/
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static void send_mipi_dcs_command(const struct ssd2828_config *cfg, u8 cmdnum)
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{
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/* Set packet size to 1 (a single command with no parameters) */
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write_hw_register(cfg, SSD2828_PSCR1, 1);
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/* Send the command */
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write_hw_register(cfg, SSD2828_PDR, cmdnum);
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}
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/*
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* Reset SSD2828
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*/
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static void ssd2828_reset(const struct ssd2828_config *cfg)
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{
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/* RESET needs 10 milliseconds according to the datasheet */
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gpio_set_value(cfg->reset_pin, 0);
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mdelay(10);
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gpio_set_value(cfg->reset_pin, 1);
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mdelay(10);
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}
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static int ssd2828_enable_gpio(const struct ssd2828_config *cfg)
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{
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if (gpio_request(cfg->csx_pin, "ssd2828_csx")) {
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printf("SSD2828: request for 'ssd2828_csx' pin failed\n");
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return 1;
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}
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if (gpio_request(cfg->sck_pin, "ssd2828_sck")) {
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gpio_free(cfg->csx_pin);
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printf("SSD2828: request for 'ssd2828_sck' pin failed\n");
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return 1;
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}
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if (gpio_request(cfg->sdi_pin, "ssd2828_sdi")) {
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gpio_free(cfg->csx_pin);
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gpio_free(cfg->sck_pin);
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printf("SSD2828: request for 'ssd2828_sdi' pin failed\n");
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return 1;
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}
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if (gpio_request(cfg->reset_pin, "ssd2828_reset")) {
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gpio_free(cfg->csx_pin);
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gpio_free(cfg->sck_pin);
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gpio_free(cfg->sdi_pin);
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printf("SSD2828: request for 'ssd2828_reset' pin failed\n");
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return 1;
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}
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if (cfg->sdo_pin != -1 && gpio_request(cfg->sdo_pin, "ssd2828_sdo")) {
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gpio_free(cfg->csx_pin);
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gpio_free(cfg->sck_pin);
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gpio_free(cfg->sdi_pin);
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gpio_free(cfg->reset_pin);
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printf("SSD2828: request for 'ssd2828_sdo' pin failed\n");
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return 1;
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}
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gpio_direction_output(cfg->reset_pin, 0);
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gpio_direction_output(cfg->csx_pin, 1);
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gpio_direction_output(cfg->sck_pin, 1);
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gpio_direction_output(cfg->sdi_pin, 1);
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if (cfg->sdo_pin != -1)
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gpio_direction_input(cfg->sdo_pin);
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return 0;
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}
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static int ssd2828_free_gpio(const struct ssd2828_config *cfg)
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{
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gpio_free(cfg->csx_pin);
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gpio_free(cfg->sck_pin);
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gpio_free(cfg->sdi_pin);
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gpio_free(cfg->reset_pin);
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if (cfg->sdo_pin != -1)
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gpio_free(cfg->sdo_pin);
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return 1;
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}
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/*
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* PLL configuration register settings.
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*
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* See the "PLL Configuration Register Description" in the SSD2828 datasheet.
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*/
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static u32 construct_pll_config(u32 desired_pll_freq_kbps,
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u32 reference_freq_khz)
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{
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u32 div_factor = 1, mul_factor, fr = 0;
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u32 output_freq_kbps;
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/* The intermediate clock after division can't be less than 5MHz */
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while (reference_freq_khz / (div_factor + 1) >= 5000)
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div_factor++;
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if (div_factor > 31)
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div_factor = 31;
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mul_factor = DIV_ROUND_UP(desired_pll_freq_kbps * div_factor,
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reference_freq_khz);
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output_freq_kbps = reference_freq_khz * mul_factor / div_factor;
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if (output_freq_kbps >= 501000)
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fr = 3;
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else if (output_freq_kbps >= 251000)
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fr = 2;
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else if (output_freq_kbps >= 126000)
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fr = 1;
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return (fr << 14) | (div_factor << 8) | mul_factor;
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}
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static u32 decode_pll_config(u32 pll_config, u32 reference_freq_khz)
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{
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u32 mul_factor = pll_config & 0xFF;
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u32 div_factor = (pll_config >> 8) & 0x1F;
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if (mul_factor == 0)
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mul_factor = 1;
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if (div_factor == 0)
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div_factor = 1;
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return reference_freq_khz * mul_factor / div_factor;
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}
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static int ssd2828_configure_video_interface(const struct ssd2828_config *cfg,
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const struct ctfb_res_modes *mode)
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{
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u32 val;
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/* RGB Interface Control Register 1 */
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write_hw_register(cfg, SSD2828_VICR1, (mode->vsync_len << 8) |
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(mode->hsync_len));
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/* RGB Interface Control Register 2 */
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u32 vbp = mode->vsync_len + mode->upper_margin;
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u32 hbp = mode->hsync_len + mode->left_margin;
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write_hw_register(cfg, SSD2828_VICR2, (vbp << 8) | hbp);
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/* RGB Interface Control Register 3 */
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write_hw_register(cfg, SSD2828_VICR3, (mode->lower_margin << 8) |
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(mode->right_margin));
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/* RGB Interface Control Register 4 */
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write_hw_register(cfg, SSD2828_VICR4, mode->xres);
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/* RGB Interface Control Register 5 */
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write_hw_register(cfg, SSD2828_VICR5, mode->yres);
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/* RGB Interface Control Register 6 */
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val = SSD2828_VIDEO_MODE_BURST;
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switch (cfg->ssd2828_color_depth) {
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case 16:
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val |= SSD2828_VIDEO_PIXEL_FORMAT_16BPP;
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break;
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case 18:
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val |= cfg->mipi_dsi_loosely_packed_pixel_format ?
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SSD2828_VIDEO_PIXEL_FORMAT_18BPP_LOOSELY_PACKED :
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SSD2828_VIDEO_PIXEL_FORMAT_18BPP_PACKED;
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break;
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case 24:
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val |= SSD2828_VIDEO_PIXEL_FORMAT_24BPP;
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break;
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default:
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printf("SSD2828: unsupported color depth\n");
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return 1;
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}
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write_hw_register(cfg, SSD2828_VICR6, val);
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/* Lane Configuration Register */
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write_hw_register(cfg, SSD2828_LCFR,
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cfg->mipi_dsi_number_of_data_lanes - 1);
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return 0;
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}
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int ssd2828_init(const struct ssd2828_config *cfg,
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const struct ctfb_res_modes *mode)
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{
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u32 lp_div, pll_freq_kbps, reference_freq_khz, pll_config;
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/* The LP clock speed is limited by 10MHz */
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const u32 mipi_dsi_low_power_clk_khz = 10000;
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/*
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* This is just the reset default value of CFGR register (0x301).
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* Because we are not always able to read back from SPI, have
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* it initialized here.
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*/
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u32 cfgr_reg = SSD2828_CFGR_EOT | /* EOT Packet Enable */
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SSD2828_CFGR_ECD | /* Disable ECC and CRC */
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SSD2828_CFGR_HS; /* Data lanes are in HS mode */
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/* Initialize the pins */
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if (ssd2828_enable_gpio(cfg) != 0)
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return 1;
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/* Reset the chip */
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ssd2828_reset(cfg);
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/*
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* If there is a pin to read data back from SPI, then we are lucky. Try
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* to check if SPI is configured correctly and SSD2828 is actually able
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* to talk back.
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*/
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if (cfg->sdo_pin != -1) {
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if (read_hw_register(cfg, SSD2828_DIR) != 0x2828 ||
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read_hw_register(cfg, SSD2828_CFGR) != cfgr_reg) {
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printf("SSD2828: SPI communication failed.\n");
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ssd2828_free_gpio(cfg);
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return 1;
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}
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}
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/*
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* Pick the reference clock for PLL. If we know the exact 'tx_clk'
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* clock speed, then everything is good. If not, then we can fallback
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* to 'pclk' (pixel clock from the parallel LCD interface). In the
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* case of using this fallback, it is necessary to have parallel LCD
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* already initialized and running at this point.
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*/
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reference_freq_khz = cfg->ssd2828_tx_clk_khz;
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if (reference_freq_khz == 0) {
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reference_freq_khz = mode->pixclock_khz;
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/* Use 'pclk' as the reference clock for PLL */
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cfgr_reg |= SSD2828_CFGR_CSS;
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}
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/*
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* Setup the parallel LCD timings in the appropriate registers.
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*/
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if (ssd2828_configure_video_interface(cfg, mode) != 0) {
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ssd2828_free_gpio(cfg);
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return 1;
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}
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/* Configuration Register */
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cfgr_reg &= ~SSD2828_CFGR_HS; /* Data lanes are in LP mode */
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cfgr_reg |= SSD2828_CFGR_CKE; /* Clock lane is in HS mode */
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cfgr_reg |= SSD2828_CFGR_DCS; /* Only use DCS packets */
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write_hw_register(cfg, SSD2828_CFGR, cfgr_reg);
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/* PLL Configuration Register */
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pll_config = construct_pll_config(
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cfg->mipi_dsi_bitrate_per_data_lane_mbps * 1000,
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reference_freq_khz);
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write_hw_register(cfg, SSD2828_PLCR, pll_config);
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pll_freq_kbps = decode_pll_config(pll_config, reference_freq_khz);
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lp_div = DIV_ROUND_UP(pll_freq_kbps, mipi_dsi_low_power_clk_khz * 8);
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/* VC Control Register */
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write_hw_register(cfg, SSD2828_VCR, 0);
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/* Clock Control Register */
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write_hw_register(cfg, SSD2828_CCR, SSD2828_LP_CLOCK_DIVIDER(lp_div));
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/* PLL Control Register */
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write_hw_register(cfg, SSD2828_PCR, 1); /* Enable PLL */
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/* Wait for PLL lock */
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udelay(500);
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send_mipi_dcs_command(cfg, MIPI_DCS_EXIT_SLEEP_MODE);
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mdelay(cfg->mipi_dsi_delay_after_exit_sleep_mode_ms);
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send_mipi_dcs_command(cfg, MIPI_DCS_SET_DISPLAY_ON);
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mdelay(cfg->mipi_dsi_delay_after_set_display_on_ms);
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cfgr_reg |= SSD2828_CFGR_HS; /* Enable HS mode for data lanes */
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cfgr_reg |= SSD2828_CFGR_VEN; /* Enable video pipeline */
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write_hw_register(cfg, SSD2828_CFGR, cfgr_reg);
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return 0;
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}
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