upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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429 lines
10 KiB
429 lines
10 KiB
/*
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* Copyright 2008-2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#ifdef CONFIG_PPC
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#include <asm/fsl_law.h>
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#endif
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#include <div64.h>
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#include <fsl_ddr.h>
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#include <fsl_immap.h>
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#include <asm/io.h>
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#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
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defined(CONFIG_ARM)
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#include <asm/arch/clock.h>
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#endif
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/* To avoid 64-bit full-divides, we factor this here */
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#define ULL_2E12 2000000000000ULL
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#define UL_5POW12 244140625UL
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#define UL_2POW13 (1UL << 13)
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#define ULL_8FS 0xFFFFFFFFULL
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u32 fsl_ddr_get_version(unsigned int ctrl_num)
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{
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struct ccsr_ddr __iomem *ddr;
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u32 ver_major_minor_errata;
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switch (ctrl_num) {
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case 0:
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ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
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break;
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#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
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case 1:
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ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
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break;
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#endif
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#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
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case 2:
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ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
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break;
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#endif
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#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
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case 3:
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ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
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break;
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#endif
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default:
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printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
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return 0;
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}
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ver_major_minor_errata = (ddr_in32(&ddr->ip_rev1) & 0xFFFF) << 8;
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ver_major_minor_errata |= (ddr_in32(&ddr->ip_rev2) & 0xFF00) >> 8;
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return ver_major_minor_errata;
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}
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/*
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* Round up mclk_ps to nearest 1 ps in memory controller code
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* if the error is 0.5ps or more.
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*
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* If an imprecise data rate is too high due to rounding error
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* propagation, compute a suitably rounded mclk_ps to compute
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* a working memory controller configuration.
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*/
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unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num)
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{
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unsigned int data_rate = get_ddr_freq(ctrl_num);
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unsigned int result;
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/* Round to nearest 10ps, being careful about 64-bit multiply/divide */
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unsigned long long rem, mclk_ps = ULL_2E12;
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/* Now perform the big divide, the result fits in 32-bits */
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rem = do_div(mclk_ps, data_rate);
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result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps;
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return result;
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}
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/* Convert picoseconds into DRAM clock cycles (rounding up if needed). */
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unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos)
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{
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unsigned long long clks, clks_rem;
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unsigned long data_rate = get_ddr_freq(ctrl_num);
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/* Short circuit for zero picos */
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if (!picos)
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return 0;
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/* First multiply the time by the data rate (32x32 => 64) */
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clks = picos * (unsigned long long)data_rate;
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/*
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* Now divide by 5^12 and track the 32-bit remainder, then divide
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* by 2*(2^12) using shifts (and updating the remainder).
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*/
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clks_rem = do_div(clks, UL_5POW12);
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clks_rem += (clks & (UL_2POW13-1)) * UL_5POW12;
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clks >>= 13;
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/* If we had a remainder greater than the 1ps error, then round up */
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if (clks_rem > data_rate)
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clks++;
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/* Clamp to the maximum representable value */
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if (clks > ULL_8FS)
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clks = ULL_8FS;
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return (unsigned int) clks;
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}
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unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk)
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{
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return get_memory_clk_period_ps(ctrl_num) * mclk;
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}
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#ifdef CONFIG_PPC
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void
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__fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
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unsigned int law_memctl,
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unsigned int ctrl_num)
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{
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unsigned long long base = memctl_common_params->base_address;
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unsigned long long size = memctl_common_params->total_mem;
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/*
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* If no DIMMs on this controller, do not proceed any further.
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*/
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if (!memctl_common_params->ndimms_present) {
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return;
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}
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#if !defined(CONFIG_PHYS_64BIT)
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if (base >= CONFIG_MAX_MEM_MAPPED)
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return;
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if ((base + size) >= CONFIG_MAX_MEM_MAPPED)
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size = CONFIG_MAX_MEM_MAPPED - base;
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#endif
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if (set_ddr_laws(base, size, law_memctl) < 0) {
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printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__, ctrl_num,
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law_memctl);
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return ;
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}
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debug("setup ddr law base = 0x%llx, size 0x%llx, TRGT_ID 0x%x\n",
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base, size, law_memctl);
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}
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__attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void
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fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
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unsigned int memctl_interleaved,
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unsigned int ctrl_num);
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#endif
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void fsl_ddr_set_intl3r(const unsigned int granule_size)
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{
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#ifdef CONFIG_E6500
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u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
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*mcintl3r = 0x80000000 | (granule_size & 0x1f);
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debug("Enable MCINTL3R with granule size 0x%x\n", granule_size);
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#endif
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}
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u32 fsl_ddr_get_intl3r(void)
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{
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u32 val = 0;
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#ifdef CONFIG_E6500
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u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
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val = *mcintl3r;
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#endif
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return val;
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}
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void print_ddr_info(unsigned int start_ctrl)
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{
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struct ccsr_ddr __iomem *ddr =
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(struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
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#if defined(CONFIG_E6500) && (CONFIG_SYS_NUM_DDR_CTLRS == 3)
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u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
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#endif
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#if (CONFIG_SYS_NUM_DDR_CTLRS > 1)
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uint32_t cs0_config = ddr_in32(&ddr->cs0_config);
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#endif
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uint32_t sdram_cfg = ddr_in32(&ddr->sdram_cfg);
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int cas_lat;
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#if CONFIG_SYS_NUM_DDR_CTLRS >= 2
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if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
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(start_ctrl == 1)) {
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ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR;
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sdram_cfg = ddr_in32(&ddr->sdram_cfg);
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}
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#endif
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#if CONFIG_SYS_NUM_DDR_CTLRS >= 3
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if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
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(start_ctrl == 2)) {
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ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR;
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sdram_cfg = ddr_in32(&ddr->sdram_cfg);
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}
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#endif
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if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
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puts(" (DDR not enabled)\n");
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return;
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}
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puts(" (DDR");
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switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
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SDRAM_CFG_SDRAM_TYPE_SHIFT) {
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case SDRAM_TYPE_DDR1:
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puts("1");
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break;
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case SDRAM_TYPE_DDR2:
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puts("2");
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break;
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case SDRAM_TYPE_DDR3:
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puts("3");
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break;
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case SDRAM_TYPE_DDR4:
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puts("4");
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break;
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default:
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puts("?");
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break;
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}
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if (sdram_cfg & SDRAM_CFG_32_BE)
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puts(", 32-bit");
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else if (sdram_cfg & SDRAM_CFG_16_BE)
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puts(", 16-bit");
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else
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puts(", 64-bit");
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/* Calculate CAS latency based on timing cfg values */
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cas_lat = ((ddr_in32(&ddr->timing_cfg_1) >> 16) & 0xf);
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if (fsl_ddr_get_version(0) <= 0x40400)
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cas_lat += 1;
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else
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cas_lat += 2;
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cas_lat += ((ddr_in32(&ddr->timing_cfg_3) >> 12) & 3) << 4;
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printf(", CL=%d", cas_lat >> 1);
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if (cas_lat & 0x1)
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puts(".5");
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if (sdram_cfg & SDRAM_CFG_ECC_EN)
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puts(", ECC on)");
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else
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puts(", ECC off)");
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#if (CONFIG_SYS_NUM_DDR_CTLRS == 3)
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#ifdef CONFIG_E6500
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if (*mcintl3r & 0x80000000) {
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puts("\n");
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puts(" DDR Controller Interleaving Mode: ");
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switch (*mcintl3r & 0x1f) {
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case FSL_DDR_3WAY_1KB_INTERLEAVING:
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puts("3-way 1KB");
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break;
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case FSL_DDR_3WAY_4KB_INTERLEAVING:
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puts("3-way 4KB");
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break;
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case FSL_DDR_3WAY_8KB_INTERLEAVING:
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puts("3-way 8KB");
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break;
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default:
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puts("3-way UNKNOWN");
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break;
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}
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}
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#endif
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#endif
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#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
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if ((cs0_config & 0x20000000) && (start_ctrl == 0)) {
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puts("\n");
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puts(" DDR Controller Interleaving Mode: ");
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switch ((cs0_config >> 24) & 0xf) {
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case FSL_DDR_256B_INTERLEAVING:
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puts("256B");
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break;
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case FSL_DDR_CACHE_LINE_INTERLEAVING:
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puts("cache line");
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break;
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case FSL_DDR_PAGE_INTERLEAVING:
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puts("page");
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break;
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case FSL_DDR_BANK_INTERLEAVING:
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puts("bank");
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break;
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case FSL_DDR_SUPERBANK_INTERLEAVING:
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puts("super-bank");
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break;
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default:
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puts("invalid");
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break;
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}
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}
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#endif
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if ((sdram_cfg >> 8) & 0x7f) {
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puts("\n");
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puts(" DDR Chip-Select Interleaving Mode: ");
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switch(sdram_cfg >> 8 & 0x7f) {
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case FSL_DDR_CS0_CS1_CS2_CS3:
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puts("CS0+CS1+CS2+CS3");
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break;
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case FSL_DDR_CS0_CS1:
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puts("CS0+CS1");
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break;
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case FSL_DDR_CS2_CS3:
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puts("CS2+CS3");
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break;
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case FSL_DDR_CS0_CS1_AND_CS2_CS3:
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puts("CS0+CS1 and CS2+CS3");
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break;
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default:
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puts("invalid");
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break;
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}
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}
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}
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void __weak detail_board_ddr_info(void)
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{
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print_ddr_info(0);
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}
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void board_add_ram_info(int use_default)
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{
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detail_board_ddr_info();
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}
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#ifdef CONFIG_FSL_DDR_SYNC_REFRESH
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#define DDRC_DEBUG20_INIT_DONE 0x80000000
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#define DDRC_DEBUG2_RF 0x00000040
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void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
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unsigned int last_ctrl)
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{
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unsigned int i;
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u32 ddrc_debug20;
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u32 ddrc_debug2[CONFIG_SYS_NUM_DDR_CTLRS] = {};
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u32 *ddrc_debug2_p[CONFIG_SYS_NUM_DDR_CTLRS] = {};
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struct ccsr_ddr __iomem *ddr;
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for (i = first_ctrl; i <= last_ctrl; i++) {
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switch (i) {
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case 0:
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ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
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break;
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#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
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case 1:
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ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
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break;
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#endif
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#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
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case 2:
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ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
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break;
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#endif
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#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
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case 3:
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ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
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break;
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#endif
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default:
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printf("%s unexpected ctrl = %u\n", __func__, i);
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return;
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}
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ddrc_debug20 = ddr_in32(&ddr->debug[19]);
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ddrc_debug2_p[i] = &ddr->debug[1];
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while (!(ddrc_debug20 & DDRC_DEBUG20_INIT_DONE)) {
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/* keep polling until DDRC init is done */
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udelay(100);
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ddrc_debug20 = ddr_in32(&ddr->debug[19]);
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}
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ddrc_debug2[i] = ddr_in32(&ddr->debug[1]) | DDRC_DEBUG2_RF;
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}
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/*
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* Sync refresh
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* This is put together to make sure the refresh reqeusts are sent
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* closely to each other.
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*/
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for (i = first_ctrl; i <= last_ctrl; i++)
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ddr_out32(ddrc_debug2_p[i], ddrc_debug2[i]);
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}
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#endif /* CONFIG_FSL_DDR_SYNC_REFRESH */
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void remove_unused_controllers(fsl_ddr_info_t *info)
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{
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#ifdef CONFIG_SYS_FSL_HAS_CCN504
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int i;
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u64 nodeid;
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void *hnf_sam_ctrl = (void *)(CCI_HN_F_0_BASE + CCN_HN_F_SAM_CTL);
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bool ddr0_used = false;
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bool ddr1_used = false;
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for (i = 0; i < 8; i++) {
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nodeid = in_le64(hnf_sam_ctrl) & CCN_HN_F_SAM_NODEID_MASK;
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if (nodeid == CCN_HN_F_SAM_NODEID_DDR0) {
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ddr0_used = true;
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} else if (nodeid == CCN_HN_F_SAM_NODEID_DDR1) {
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ddr1_used = true;
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} else {
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printf("Unknown nodeid in HN-F SAM control: 0x%llx\n",
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nodeid);
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}
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hnf_sam_ctrl += (CCI_HN_F_1_BASE - CCI_HN_F_0_BASE);
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}
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if (!ddr0_used && !ddr1_used) {
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printf("Invalid configuration in HN-F SAM control\n");
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return;
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}
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if (!ddr0_used && info->first_ctrl == 0) {
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info->first_ctrl = 1;
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info->num_ctrls = 1;
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debug("First DDR controller disabled\n");
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return;
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}
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if (!ddr1_used && info->first_ctrl + info->num_ctrls > 1) {
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info->num_ctrls = 1;
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debug("Second DDR controller disabled\n");
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}
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#endif
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}
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