upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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626 lines
14 KiB
626 lines
14 KiB
/*
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* sh_eth.h - Driver for Renesas SuperH ethernet controller.
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*
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* Copyright (C) 2008 - 2012 Renesas Solutions Corp.
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* Copyright (c) 2008 - 2012 Nobuhiro Iwamatsu
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* Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <netdev.h>
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#include <asm/types.h>
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#define SHETHER_NAME "sh_eth"
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#if defined(CONFIG_SH)
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/* Malloc returns addresses in the P1 area (cacheable). However we need to
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use area P2 (non-cacheable) */
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#define ADDR_TO_P2(addr) ((((int)(addr) & ~0xe0000000) | 0xa0000000))
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/* The ethernet controller needs to use physical addresses */
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#if defined(CONFIG_SH_32BIT)
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#define ADDR_TO_PHY(addr) ((((int)(addr) & ~0xe0000000) | 0x40000000))
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#else
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#define ADDR_TO_PHY(addr) ((int)(addr) & ~0xe0000000)
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#endif
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#elif defined(CONFIG_ARM)
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#ifndef inl
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#define inl readl
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#define outl writel
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#endif
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#define ADDR_TO_PHY(addr) ((int)(addr))
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#define ADDR_TO_P2(addr) (addr)
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#endif /* defined(CONFIG_SH) */
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/* base padding size is 16 */
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#ifndef CONFIG_SH_ETHER_ALIGNE_SIZE
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#define CONFIG_SH_ETHER_ALIGNE_SIZE 16
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#endif
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/* Number of supported ports */
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#define MAX_PORT_NUM 2
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/* Buffers must be big enough to hold the largest ethernet frame. Also, rx
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buffers must be a multiple of 32 bytes */
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#define MAX_BUF_SIZE (48 * 32)
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/* The number of tx descriptors must be large enough to point to 5 or more
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frames. If each frame uses 2 descriptors, at least 10 descriptors are needed.
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We use one descriptor per frame */
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#define NUM_TX_DESC 8
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/* The size of the tx descriptor is determined by how much padding is used.
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4, 20, or 52 bytes of padding can be used */
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#define TX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
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/* Tx descriptor. We always use 3 bytes of padding */
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struct tx_desc_s {
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volatile u32 td0;
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u32 td1;
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u32 td2; /* Buffer start */
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u8 padding[TX_DESC_PADDING]; /* aligned cache line size */
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};
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/* There is no limitation in the number of rx descriptors */
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#define NUM_RX_DESC 8
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/* The size of the rx descriptor is determined by how much padding is used.
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4, 20, or 52 bytes of padding can be used */
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#define RX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
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/* aligned cache line size */
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#define RX_BUF_ALIGNE_SIZE (CONFIG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32)
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/* Rx descriptor. We always use 4 bytes of padding */
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struct rx_desc_s {
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volatile u32 rd0;
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volatile u32 rd1;
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u32 rd2; /* Buffer start */
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u8 padding[TX_DESC_PADDING]; /* aligned cache line size */
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};
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struct sh_eth_info {
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struct tx_desc_s *tx_desc_alloc;
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struct tx_desc_s *tx_desc_base;
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struct tx_desc_s *tx_desc_cur;
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struct rx_desc_s *rx_desc_alloc;
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struct rx_desc_s *rx_desc_base;
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struct rx_desc_s *rx_desc_cur;
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u8 *rx_buf_alloc;
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u8 *rx_buf_base;
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u8 mac_addr[6];
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u8 phy_addr;
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struct eth_device *dev;
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struct phy_device *phydev;
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void __iomem *iobase;
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};
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struct sh_eth_dev {
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int port;
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struct sh_eth_info port_info[MAX_PORT_NUM];
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};
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/* from linux/drivers/net/ethernet/renesas/sh_eth.h */
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enum {
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/* E-DMAC registers */
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EDSR = 0,
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EDMR,
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EDTRR,
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EDRRR,
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EESR,
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EESIPR,
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TDLAR,
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TDFAR,
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TDFXR,
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TDFFR,
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RDLAR,
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RDFAR,
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RDFXR,
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RDFFR,
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TRSCER,
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RMFCR,
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TFTR,
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FDR,
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RMCR,
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EDOCR,
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TFUCR,
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RFOCR,
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FCFTR,
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RPADIR,
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TRIMD,
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RBWAR,
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TBRAR,
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/* Ether registers */
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ECMR,
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ECSR,
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ECSIPR,
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PIR,
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PSR,
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RDMLR,
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PIPR,
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RFLR,
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IPGR,
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APR,
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MPR,
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PFTCR,
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PFRCR,
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RFCR,
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RFCF,
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TPAUSER,
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TPAUSECR,
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BCFR,
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BCFRR,
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GECMR,
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BCULR,
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MAHR,
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MALR,
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TROCR,
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CDCR,
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LCCR,
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CNDCR,
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CEFCR,
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FRECR,
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TSFRCR,
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TLFRCR,
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CERCR,
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CEECR,
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RMIIMR, /* R8A7790 */
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MAFCR,
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RTRATE,
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CSMR,
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RMII_MII,
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/* This value must be written at last. */
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SH_ETH_MAX_REGISTER_OFFSET,
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};
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static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
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[EDSR] = 0x0000,
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[EDMR] = 0x0400,
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[EDTRR] = 0x0408,
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[EDRRR] = 0x0410,
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[EESR] = 0x0428,
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[EESIPR] = 0x0430,
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[TDLAR] = 0x0010,
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[TDFAR] = 0x0014,
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[TDFXR] = 0x0018,
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[TDFFR] = 0x001c,
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[RDLAR] = 0x0030,
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[RDFAR] = 0x0034,
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[RDFXR] = 0x0038,
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[RDFFR] = 0x003c,
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[TRSCER] = 0x0438,
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[RMFCR] = 0x0440,
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[TFTR] = 0x0448,
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[FDR] = 0x0450,
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[RMCR] = 0x0458,
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[RPADIR] = 0x0460,
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[FCFTR] = 0x0468,
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[CSMR] = 0x04E4,
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[ECMR] = 0x0500,
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[ECSR] = 0x0510,
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[ECSIPR] = 0x0518,
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[PIR] = 0x0520,
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[PSR] = 0x0528,
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[PIPR] = 0x052c,
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[RFLR] = 0x0508,
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[APR] = 0x0554,
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[MPR] = 0x0558,
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[PFTCR] = 0x055c,
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[PFRCR] = 0x0560,
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[TPAUSER] = 0x0564,
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[GECMR] = 0x05b0,
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[BCULR] = 0x05b4,
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[MAHR] = 0x05c0,
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[MALR] = 0x05c8,
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[TROCR] = 0x0700,
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[CDCR] = 0x0708,
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[LCCR] = 0x0710,
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[CEFCR] = 0x0740,
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[FRECR] = 0x0748,
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[TSFRCR] = 0x0750,
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[TLFRCR] = 0x0758,
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[RFCR] = 0x0760,
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[CERCR] = 0x0768,
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[CEECR] = 0x0770,
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[MAFCR] = 0x0778,
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[RMII_MII] = 0x0790,
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};
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static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
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[ECMR] = 0x0100,
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[RFLR] = 0x0108,
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[ECSR] = 0x0110,
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[ECSIPR] = 0x0118,
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[PIR] = 0x0120,
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[PSR] = 0x0128,
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[RDMLR] = 0x0140,
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[IPGR] = 0x0150,
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[APR] = 0x0154,
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[MPR] = 0x0158,
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[TPAUSER] = 0x0164,
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[RFCF] = 0x0160,
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[TPAUSECR] = 0x0168,
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[BCFRR] = 0x016c,
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[MAHR] = 0x01c0,
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[MALR] = 0x01c8,
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[TROCR] = 0x01d0,
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[CDCR] = 0x01d4,
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[LCCR] = 0x01d8,
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[CNDCR] = 0x01dc,
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[CEFCR] = 0x01e4,
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[FRECR] = 0x01e8,
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[TSFRCR] = 0x01ec,
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[TLFRCR] = 0x01f0,
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[RFCR] = 0x01f4,
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[MAFCR] = 0x01f8,
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[RTRATE] = 0x01fc,
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[EDMR] = 0x0000,
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[EDTRR] = 0x0008,
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[EDRRR] = 0x0010,
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[TDLAR] = 0x0018,
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[RDLAR] = 0x0020,
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[EESR] = 0x0028,
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[EESIPR] = 0x0030,
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[TRSCER] = 0x0038,
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[RMFCR] = 0x0040,
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[TFTR] = 0x0048,
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[FDR] = 0x0050,
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[RMCR] = 0x0058,
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[TFUCR] = 0x0064,
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[RFOCR] = 0x0068,
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[RMIIMR] = 0x006C,
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[FCFTR] = 0x0070,
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[RPADIR] = 0x0078,
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[TRIMD] = 0x007c,
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[RBWAR] = 0x00c8,
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[RDFAR] = 0x00cc,
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[TBRAR] = 0x00d4,
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[TDFAR] = 0x00d8,
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};
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/* Register Address */
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#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
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#define SH_ETH_TYPE_GETHER
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#define BASE_IO_ADDR 0xfee00000
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#elif defined(CONFIG_CPU_SH7757) || \
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defined(CONFIG_CPU_SH7752) || \
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defined(CONFIG_CPU_SH7753)
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#if defined(CONFIG_SH_ETHER_USE_GETHER)
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#define SH_ETH_TYPE_GETHER
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#define BASE_IO_ADDR 0xfee00000
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#else
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#define SH_ETH_TYPE_ETHER
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#define BASE_IO_ADDR 0xfef00000
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#endif
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#elif defined(CONFIG_CPU_SH7724)
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#define SH_ETH_TYPE_ETHER
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#define BASE_IO_ADDR 0xA4600000
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#elif defined(CONFIG_R8A7740)
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#define SH_ETH_TYPE_GETHER
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#define BASE_IO_ADDR 0xE9A00000
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#elif defined(CONFIG_RCAR_GEN2)
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#define SH_ETH_TYPE_ETHER
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#define BASE_IO_ADDR 0xEE700200
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#elif defined(CONFIG_R7S72100)
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#define SH_ETH_TYPE_RZ
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#define BASE_IO_ADDR 0xE8203000
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#endif
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/*
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* Register's bits
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* Copy from Linux driver source code
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*/
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#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
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/* EDSR */
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enum EDSR_BIT {
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EDSR_ENT = 0x01, EDSR_ENR = 0x02,
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};
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#define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
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#endif
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/* EDMR */
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enum DMAC_M_BIT {
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EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
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#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
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EDMR_SRST = 0x03, /* Receive/Send reset */
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EMDR_DESC_R = 0x30, /* Descriptor reserve size */
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EDMR_EL = 0x40, /* Litte endian */
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#elif defined(SH_ETH_TYPE_ETHER)
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EDMR_SRST = 0x01,
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EMDR_DESC_R = 0x30, /* Descriptor reserve size */
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EDMR_EL = 0x40, /* Litte endian */
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#else
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EDMR_SRST = 0x01,
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#endif
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};
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#if CONFIG_SH_ETHER_ALIGNE_SIZE == 64
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# define EMDR_DESC EDMR_DL1
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#elif CONFIG_SH_ETHER_ALIGNE_SIZE == 32
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# define EMDR_DESC EDMR_DL0
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#elif CONFIG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */
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# define EMDR_DESC 0
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#endif
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/* RFLR */
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#define RFLR_RFL_MIN 0x05EE /* Recv Frame length 1518 byte */
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/* EDTRR */
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enum DMAC_T_BIT {
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#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
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EDTRR_TRNS = 0x03,
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#else
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EDTRR_TRNS = 0x01,
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#endif
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};
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/* GECMR */
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enum GECMR_BIT {
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#if defined(CONFIG_CPU_SH7757) || \
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defined(CONFIG_CPU_SH7752) || \
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defined(CONFIG_CPU_SH7753)
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GECMR_1000B = 0x20, GECMR_100B = 0x01, GECMR_10B = 0x00,
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#else
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GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00,
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#endif
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};
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/* EDRRR*/
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enum EDRRR_R_BIT {
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EDRRR_R = 0x01,
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};
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/* TPAUSER */
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enum TPAUSER_BIT {
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TPAUSER_TPAUSE = 0x0000ffff,
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TPAUSER_UNLIMITED = 0,
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};
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/* BCFR */
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enum BCFR_BIT {
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BCFR_RPAUSE = 0x0000ffff,
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BCFR_UNLIMITED = 0,
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};
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/* PIR */
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enum PIR_BIT {
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PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
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};
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/* PSR */
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enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
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/* EESR */
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enum EESR_BIT {
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#if defined(SH_ETH_TYPE_ETHER)
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EESR_TWB = 0x40000000,
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#else
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EESR_TWB = 0xC0000000,
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EESR_TC1 = 0x20000000,
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EESR_TUC = 0x10000000,
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EESR_ROC = 0x80000000,
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#endif
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EESR_TABT = 0x04000000,
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EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000,
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#if defined(SH_ETH_TYPE_ETHER)
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EESR_ADE = 0x00800000,
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#endif
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EESR_ECI = 0x00400000,
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EESR_FTC = 0x00200000, EESR_TDE = 0x00100000,
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EESR_TFE = 0x00080000, EESR_FRC = 0x00040000,
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EESR_RDE = 0x00020000, EESR_RFE = 0x00010000,
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#if defined(SH_ETH_TYPE_ETHER)
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EESR_CND = 0x00000800,
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#endif
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EESR_DLC = 0x00000400,
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EESR_CD = 0x00000200, EESR_RTO = 0x00000100,
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EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040,
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EESR_CELF = 0x00000020, EESR_RRF = 0x00000010,
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EESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004,
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EESR_PRE = 0x00000002, EESR_CERF = 0x00000001,
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};
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#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
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# define TX_CHECK (EESR_TC1 | EESR_FTC)
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# define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
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| EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI)
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# define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE)
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#else
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# define TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO)
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# define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
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| EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI)
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# define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE)
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#endif
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/* EESIPR */
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enum DMAC_IM_BIT {
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DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
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DMAC_M_RABT = 0x02000000,
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DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
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DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
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DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
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DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
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DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
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DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
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DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
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DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
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DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
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DMAC_M_RINT1 = 0x00000001,
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};
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/* Receive descriptor bit */
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enum RD_STS_BIT {
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RD_RACT = 0x80000000, RD_RDLE = 0x40000000,
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RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
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RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
|
|
RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
|
|
RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
|
|
RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
|
|
RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
|
|
RD_RFS1 = 0x00000001,
|
|
};
|
|
#define RDF1ST RD_RFP1
|
|
#define RDFEND RD_RFP0
|
|
#define RD_RFP (RD_RFP1|RD_RFP0)
|
|
|
|
/* RDFFR*/
|
|
enum RDFFR_BIT {
|
|
RDFFR_RDLF = 0x01,
|
|
};
|
|
|
|
/* FCFTR */
|
|
enum FCFTR_BIT {
|
|
FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
|
|
FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
|
|
FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
|
|
};
|
|
#define FIFO_F_D_RFF (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0)
|
|
#define FIFO_F_D_RFD (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0)
|
|
|
|
/* Transfer descriptor bit */
|
|
enum TD_STS_BIT {
|
|
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER) || \
|
|
defined(SH_ETH_TYPE_RZ)
|
|
TD_TACT = 0x80000000,
|
|
#else
|
|
TD_TACT = 0x7fffffff,
|
|
#endif
|
|
TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
|
|
TD_TFP0 = 0x10000000,
|
|
};
|
|
#define TDF1ST TD_TFP1
|
|
#define TDFEND TD_TFP0
|
|
#define TD_TFP (TD_TFP1|TD_TFP0)
|
|
|
|
/* RMCR */
|
|
enum RECV_RST_BIT { RMCR_RST = 0x01, };
|
|
/* ECMR */
|
|
enum FELIC_MODE_BIT {
|
|
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
|
|
ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
|
|
ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
|
|
#endif
|
|
ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
|
|
ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
|
|
ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
|
|
ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002,
|
|
ECMR_PRM = 0x00000001,
|
|
#ifdef CONFIG_CPU_SH7724
|
|
ECMR_RTM = 0x00000010,
|
|
#elif defined(CONFIG_RCAR_GEN2)
|
|
ECMR_RTM = 0x00000004,
|
|
#endif
|
|
|
|
};
|
|
|
|
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
|
|
#define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | \
|
|
ECMR_RXF | ECMR_TXF | ECMR_MCT)
|
|
#elif defined(SH_ETH_TYPE_ETHER)
|
|
#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF)
|
|
#else
|
|
#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT)
|
|
#endif
|
|
|
|
/* ECSR */
|
|
enum ECSR_STATUS_BIT {
|
|
#if defined(SH_ETH_TYPE_ETHER)
|
|
ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
|
|
#endif
|
|
ECSR_LCHNG = 0x04,
|
|
ECSR_MPD = 0x02, ECSR_ICD = 0x01,
|
|
};
|
|
|
|
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
|
|
# define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP)
|
|
#else
|
|
# define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \
|
|
ECSR_LCHNG | ECSR_ICD | ECSIPR_MPDIP)
|
|
#endif
|
|
|
|
/* ECSIPR */
|
|
enum ECSIPR_STATUS_MASK_BIT {
|
|
#if defined(SH_ETH_TYPE_ETHER)
|
|
ECSIPR_BRCRXIP = 0x20,
|
|
ECSIPR_PSRTOIP = 0x10,
|
|
#elif defined(SH_ETY_TYPE_GETHER)
|
|
ECSIPR_PSRTOIP = 0x10,
|
|
ECSIPR_PHYIP = 0x08,
|
|
#endif
|
|
ECSIPR_LCHNGIP = 0x04,
|
|
ECSIPR_MPDIP = 0x02,
|
|
ECSIPR_ICDIP = 0x01,
|
|
};
|
|
|
|
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
|
|
# define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
|
|
#else
|
|
# define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \
|
|
ECSIPR_ICDIP | ECSIPR_MPDIP)
|
|
#endif
|
|
|
|
/* APR */
|
|
enum APR_BIT {
|
|
APR_AP = 0x00000004,
|
|
};
|
|
|
|
/* MPR */
|
|
enum MPR_BIT {
|
|
MPR_MP = 0x00000006,
|
|
};
|
|
|
|
/* TRSCER */
|
|
enum DESC_I_BIT {
|
|
DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
|
|
DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
|
|
DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
|
|
DESC_I_RINT1 = 0x0001,
|
|
};
|
|
|
|
/* RPADIR */
|
|
enum RPADIR_BIT {
|
|
RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
|
|
RPADIR_PADR = 0x0003f,
|
|
};
|
|
|
|
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
|
|
# define RPADIR_INIT (0x00)
|
|
#else
|
|
# define RPADIR_INIT (RPADIR_PADS1)
|
|
#endif
|
|
|
|
/* FDR */
|
|
enum FIFO_SIZE_BIT {
|
|
FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
|
|
};
|
|
|
|
static inline unsigned long sh_eth_reg_addr(struct sh_eth_info *port,
|
|
int enum_index)
|
|
{
|
|
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
|
|
const u16 *reg_offset = sh_eth_offset_gigabit;
|
|
#elif defined(SH_ETH_TYPE_ETHER)
|
|
const u16 *reg_offset = sh_eth_offset_fast_sh4;
|
|
#else
|
|
#error
|
|
#endif
|
|
return (unsigned long)port->iobase + reg_offset[enum_index];
|
|
}
|
|
|
|
static inline void sh_eth_write(struct sh_eth_info *port, unsigned long data,
|
|
int enum_index)
|
|
{
|
|
outl(data, sh_eth_reg_addr(port, enum_index));
|
|
}
|
|
|
|
static inline unsigned long sh_eth_read(struct sh_eth_info *port,
|
|
int enum_index)
|
|
{
|
|
return inl(sh_eth_reg_addr(port, enum_index));
|
|
}
|
|
|