upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
319 lines
9.4 KiB
319 lines
9.4 KiB
/*
|
|
* (C) Copyright 2010
|
|
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
|
|
*
|
|
* This program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License as
|
|
* published by the Free Software Foundation; either version 2 of
|
|
* the License, or (at your option) any later version.
|
|
*/
|
|
|
|
#ifndef __CONFIG_KM83XX_H
|
|
#define __CONFIG_KM83XX_H
|
|
|
|
/* include common defines/options for all Keymile boards */
|
|
#include "keymile-common.h"
|
|
#include "km-powerpc.h"
|
|
|
|
#define MTDIDS_DEFAULT "nor0=boot"
|
|
#define MTDPARTS_DEFAULT "mtdparts=" \
|
|
"boot:" \
|
|
"768k(u-boot)," \
|
|
"128k(env)," \
|
|
"128k(envred)," \
|
|
"-(" CONFIG_KM_UBI_PARTITION_NAME ")"
|
|
|
|
#define CONFIG_MISC_INIT_R
|
|
/*
|
|
* System Clock Setup
|
|
*/
|
|
#define CONFIG_83XX_CLKIN 66000000
|
|
#define CONFIG_SYS_CLK_FREQ 66000000
|
|
#define CONFIG_83XX_PCICLK 66000000
|
|
|
|
/*
|
|
* IMMR new address
|
|
*/
|
|
#define CONFIG_SYS_IMMR 0xE0000000
|
|
|
|
/*
|
|
* Bus Arbitration Configuration Register (ACR)
|
|
*/
|
|
#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
|
|
#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
|
|
#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
|
|
#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
|
|
|
|
/*
|
|
* DDR Setup
|
|
*/
|
|
#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
|
|
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
|
|
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
|
|
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
|
|
DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
|
|
|
|
#define CFG_83XX_DDR_USES_CS0
|
|
|
|
/*
|
|
* Manually set up DDR parameters
|
|
*/
|
|
#define CONFIG_DDR_II
|
|
#define CONFIG_SYS_DDR_SIZE 2048 /* MB */
|
|
|
|
/*
|
|
* The reserved memory
|
|
*/
|
|
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
|
|
#define CONFIG_SYS_FLASH_BASE 0xF0000000
|
|
|
|
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
|
|
#define CONFIG_SYS_RAMBOOT
|
|
#endif
|
|
|
|
/* Reserve 768 kB for Mon */
|
|
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
|
|
|
|
/*
|
|
* Initial RAM Base Address Setup
|
|
*/
|
|
#define CONFIG_SYS_INIT_RAM_LOCK
|
|
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
|
|
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
|
|
#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
|
|
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
|
|
GENERATED_GBL_DATA_SIZE)
|
|
|
|
/*
|
|
* Init Local Bus Memory Controller:
|
|
*
|
|
* Bank Bus Machine PortSz Size Device
|
|
* ---- --- ------- ------ ----- ------
|
|
* 0 Local GPCM 16 bit 256MB FLASH
|
|
* 1 Local GPCM 8 bit 128MB GPIO/PIGGY
|
|
*
|
|
*/
|
|
/*
|
|
* FLASH on the Local Bus
|
|
*/
|
|
#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
|
|
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
|
|
#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
|
|
#define CONFIG_SYS_FLASH_PROTECTION
|
|
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
|
|
|
|
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
|
|
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001b /* 256MB window size */
|
|
|
|
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
|
|
(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
|
|
BR_V)
|
|
|
|
#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
|
|
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
|
|
OR_GPCM_SCY_5 | \
|
|
OR_GPCM_TRLX | OR_GPCM_EAD)
|
|
|
|
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
|
|
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
|
|
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
|
|
|
|
/*
|
|
* PRIO1/PIGGY on the local bus CS1
|
|
*/
|
|
/* Window base at flash base */
|
|
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE
|
|
#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001A /* 128MB window size */
|
|
|
|
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \
|
|
(1 << BR_PS_SHIFT) | /* 8 bit port size */ \
|
|
BR_V)
|
|
#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
|
|
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
|
|
OR_GPCM_SCY_2 | \
|
|
OR_GPCM_TRLX | OR_GPCM_EAD)
|
|
|
|
/*
|
|
* Serial Port
|
|
*/
|
|
#define CONFIG_CONS_INDEX 1
|
|
#define CONFIG_SYS_NS16550
|
|
#define CONFIG_SYS_NS16550_SERIAL
|
|
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
|
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
|
|
|
|
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
|
|
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
|
|
|
|
/* Pass open firmware flat tree */
|
|
#define CONFIG_OF_LIBFDT
|
|
#define CONFIG_OF_BOARD_SETUP
|
|
#define CONFIG_OF_STDOUT_VIA_ALIAS
|
|
|
|
#ifndef CONFIG_NET_MULTI
|
|
#define CONFIG_NET_MULTI
|
|
#endif
|
|
/*
|
|
* QE UEC ethernet configuration
|
|
*/
|
|
#define CONFIG_UEC_ETH
|
|
#define CONFIG_ETHPRIME "UEC0"
|
|
|
|
#define CONFIG_UEC_ETH1 /* GETH1 */
|
|
#define UEC_VERBOSE_DEBUG 1
|
|
|
|
#ifdef CONFIG_UEC_ETH1
|
|
#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
|
|
#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
|
|
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
|
|
#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
|
|
#define CONFIG_SYS_UEC1_PHY_ADDR 0
|
|
#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
|
|
#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
|
|
#endif
|
|
|
|
/*
|
|
* Environment
|
|
*/
|
|
|
|
#ifndef CONFIG_SYS_RAMBOOT
|
|
#define CONFIG_ENV_IS_IN_FLASH
|
|
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
|
|
CONFIG_SYS_MONITOR_LEN)
|
|
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
|
|
#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN)
|
|
|
|
/* Address and size of Redundant Environment Sector */
|
|
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
|
|
CONFIG_ENV_SECT_SIZE)
|
|
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
|
|
|
|
#else /* CFG_SYS_RAMBOOT */
|
|
#define CONFIG_SYS_NO_FLASH /* Flash is not usable now */
|
|
#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
|
|
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
|
|
#define CONFIG_ENV_SIZE 0x2000
|
|
#endif /* CFG_SYS_RAMBOOT */
|
|
|
|
/* I2C */
|
|
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
|
#define CONFIG_FSL_I2C
|
|
#define CONFIG_SYS_I2C_SPEED 200000 /* I2C speed and slave address */
|
|
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
|
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
|
|
|
/* I2C SYSMON (LM75, AD7414 is almost compatible) */
|
|
#define CONFIG_DTT_LM75 /* ON Semi's LM75 */
|
|
#define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */
|
|
#define CONFIG_SYS_DTT_MAX_TEMP 70
|
|
#define CONFIG_SYS_DTT_LOW_TEMP -30
|
|
#define CONFIG_SYS_DTT_HYSTERESIS 3
|
|
#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
|
|
|
|
#if defined(CONFIG_CMD_NAND)
|
|
#define CONFIG_NAND_KMETER1
|
|
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
|
#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE
|
|
#endif
|
|
|
|
#if defined(CONFIG_PCI)
|
|
#define CONFIG_CMD_PCI
|
|
#endif
|
|
|
|
/*
|
|
* For booting Linux, the board info and command line data
|
|
* have to be in the first 8 MB of memory, since this is
|
|
* the maximum mapped by the Linux kernel during initialization.
|
|
*/
|
|
#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
|
|
|
|
/*
|
|
* Core HID Setup
|
|
*/
|
|
#define CONFIG_SYS_HID0_INIT 0x000000000
|
|
#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
|
|
HID0_ENABLE_INSTRUCTION_CACHE)
|
|
#define CONFIG_SYS_HID2 HID2_HBE
|
|
|
|
/*
|
|
* MMU Setup
|
|
*/
|
|
|
|
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
|
|
|
|
/* DDR: cache cacheable */
|
|
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
|
|
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
|
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
|
|
BATU_VS | BATU_VP)
|
|
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
|
|
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
|
|
|
|
/* IMMRBAR & PCI IO: cache-inhibit and guarded */
|
|
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
|
|
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
|
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \
|
|
| BATU_VP)
|
|
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
|
|
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
|
|
|
|
/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */
|
|
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_10 | \
|
|
BATL_MEMCOHERENCE)
|
|
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \
|
|
BATU_VS | BATU_VP)
|
|
#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_10 | \
|
|
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
|
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
|
|
|
|
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
|
|
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
|
|
BATL_MEMCOHERENCE)
|
|
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \
|
|
BATU_VS | BATU_VP)
|
|
#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
|
|
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
|
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
|
|
|
|
/* Stack in dcache: cacheable, no memory coherence */
|
|
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
|
|
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
|
|
BATU_VS | BATU_VP)
|
|
#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
|
|
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
|
|
|
|
/*
|
|
* Internal Definitions
|
|
*/
|
|
#define BOOTFLASH_START 0xF0000000
|
|
|
|
#define CONFIG_KM_CONSOLE_TTY "ttyS0"
|
|
|
|
/*
|
|
* Environment Configuration
|
|
*/
|
|
#define CONFIG_ENV_OVERWRITE
|
|
#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
|
|
#define CONFIG_KM_DEF_ENV "km-common=empty\0"
|
|
#endif
|
|
|
|
#ifndef CONFIG_KM_DEF_ARCH
|
|
#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
|
|
#endif
|
|
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
CONFIG_KM_DEF_ENV \
|
|
CONFIG_KM_DEF_ARCH \
|
|
"dtt_bus=pca9547:70:a\0" \
|
|
"EEprom_ivm=pca9547:70:9\0" \
|
|
"newenv=" \
|
|
"prot off 0xF00C0000 +0x40000 && " \
|
|
"era 0xF00C0000 +0x40000\0" \
|
|
"unlock=yes\0" \
|
|
""
|
|
|
|
#if defined(CONFIG_UEC_ETH)
|
|
#define CONFIG_HAS_ETH0
|
|
#endif
|
|
|
|
#endif /* __CONFIG_KM83XX_H */
|
|
|