upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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416 lines
10 KiB
416 lines
10 KiB
/*
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* Porting to u-boot:
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*
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* (C) Copyright 2010
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* Stefano Babic, DENX Software Engineering, sbabic@denx.de
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*
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* Linux IPU driver for MX51:
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*
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* (C) Copyright 2005-2009 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __IPU_REGS_INCLUDED__
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#define __IPU_REGS_INCLUDED__
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#define IPU_DISP0_BASE 0x00000000
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#define IPU_MCU_T_DEFAULT 8
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#define IPU_DISP1_BASE (IPU_MCU_T_DEFAULT << 25)
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#define IPU_CM_REG_BASE 0x00000000
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#define IPU_STAT_REG_BASE 0x00000200
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#define IPU_IDMAC_REG_BASE 0x00008000
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#define IPU_ISP_REG_BASE 0x00010000
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#define IPU_DP_REG_BASE 0x00018000
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#define IPU_IC_REG_BASE 0x00020000
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#define IPU_IRT_REG_BASE 0x00028000
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#define IPU_CSI0_REG_BASE 0x00030000
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#define IPU_CSI1_REG_BASE 0x00038000
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#define IPU_DI0_REG_BASE 0x00040000
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#define IPU_DI1_REG_BASE 0x00048000
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#define IPU_SMFC_REG_BASE 0x00050000
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#define IPU_DC_REG_BASE 0x00058000
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#define IPU_DMFC_REG_BASE 0x00060000
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#define IPU_VDI_REG_BASE 0x00680000
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#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
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#define IPU_CPMEM_REG_BASE 0x01000000
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#define IPU_LUT_REG_BASE 0x01020000
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#define IPU_SRM_REG_BASE 0x01040000
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#define IPU_TPM_REG_BASE 0x01060000
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#define IPU_DC_TMPL_REG_BASE 0x01080000
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#define IPU_ISP_TBPR_REG_BASE 0x010C0000
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#elif defined(CONFIG_MX6)
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#define IPU_CPMEM_REG_BASE 0x00100000
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#define IPU_LUT_REG_BASE 0x00120000
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#define IPU_SRM_REG_BASE 0x00140000
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#define IPU_TPM_REG_BASE 0x00160000
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#define IPU_DC_TMPL_REG_BASE 0x00180000
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#define IPU_ISP_TBPR_REG_BASE 0x001C0000
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#endif
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#define IPU_CTRL_BASE_ADDR (IPU_SOC_BASE_ADDR + IPU_SOC_OFFSET)
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extern u32 *ipu_dc_tmpl_reg;
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#define DC_EVT_NF 0
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#define DC_EVT_NL 1
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#define DC_EVT_EOF 2
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#define DC_EVT_NFIELD 3
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#define DC_EVT_EOL 4
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#define DC_EVT_EOFIELD 5
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#define DC_EVT_NEW_ADDR 6
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#define DC_EVT_NEW_CHAN 7
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#define DC_EVT_NEW_DATA 8
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#define DC_EVT_NEW_ADDR_W_0 0
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#define DC_EVT_NEW_ADDR_W_1 1
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#define DC_EVT_NEW_CHAN_W_0 2
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#define DC_EVT_NEW_CHAN_W_1 3
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#define DC_EVT_NEW_DATA_W_0 4
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#define DC_EVT_NEW_DATA_W_1 5
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#define DC_EVT_NEW_ADDR_R_0 6
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#define DC_EVT_NEW_ADDR_R_1 7
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#define DC_EVT_NEW_CHAN_R_0 8
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#define DC_EVT_NEW_CHAN_R_1 9
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#define DC_EVT_NEW_DATA_R_0 10
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#define DC_EVT_NEW_DATA_R_1 11
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/* Software reset for ipu */
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#define SW_IPU_RST 8
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enum {
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IPU_CONF_DP_EN = 0x00000020,
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IPU_CONF_DI0_EN = 0x00000040,
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IPU_CONF_DI1_EN = 0x00000080,
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IPU_CONF_DMFC_EN = 0x00000400,
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IPU_CONF_DC_EN = 0x00000200,
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DI0_COUNTER_RELEASE = 0x01000000,
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DI1_COUNTER_RELEASE = 0x02000000,
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DI_DW_GEN_ACCESS_SIZE_OFFSET = 24,
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DI_DW_GEN_COMPONENT_SIZE_OFFSET = 16,
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DI_GEN_DI_CLK_EXT = 0x100000,
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DI_GEN_POLARITY_1 = 0x00000001,
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DI_GEN_POLARITY_2 = 0x00000002,
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DI_GEN_POLARITY_3 = 0x00000004,
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DI_GEN_POLARITY_4 = 0x00000008,
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DI_GEN_POLARITY_5 = 0x00000010,
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DI_GEN_POLARITY_6 = 0x00000020,
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DI_GEN_POLARITY_7 = 0x00000040,
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DI_GEN_POLARITY_8 = 0x00000080,
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DI_GEN_POL_CLK = 0x20000,
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DI_POL_DRDY_DATA_POLARITY = 0x00000080,
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DI_POL_DRDY_POLARITY_15 = 0x00000010,
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DI_VSYNC_SEL_OFFSET = 13,
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DC_WR_CH_CONF_FIELD_MODE = 0x00000200,
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DC_WR_CH_CONF_PROG_TYPE_OFFSET = 5,
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DC_WR_CH_CONF_PROG_TYPE_MASK = 0x000000E0,
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DC_WR_CH_CONF_PROG_DI_ID = 0x00000004,
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DC_WR_CH_CONF_PROG_DISP_ID_OFFSET = 3,
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DC_WR_CH_CONF_PROG_DISP_ID_MASK = 0x00000018,
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DP_COM_CONF_FG_EN = 0x00000001,
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DP_COM_CONF_GWSEL = 0x00000002,
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DP_COM_CONF_GWAM = 0x00000004,
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DP_COM_CONF_GWCKE = 0x00000008,
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DP_COM_CONF_CSC_DEF_MASK = 0x00000300,
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DP_COM_CONF_CSC_DEF_OFFSET = 8,
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DP_COM_CONF_CSC_DEF_FG = 0x00000300,
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DP_COM_CONF_CSC_DEF_BG = 0x00000200,
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DP_COM_CONF_CSC_DEF_BOTH = 0x00000100,
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DP_COM_CONF_GAMMA_EN = 0x00001000,
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DP_COM_CONF_GAMMA_YUV_EN = 0x00002000,
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};
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enum di_pins {
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DI_PIN11 = 0,
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DI_PIN12 = 1,
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DI_PIN13 = 2,
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DI_PIN14 = 3,
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DI_PIN15 = 4,
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DI_PIN16 = 5,
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DI_PIN17 = 6,
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DI_PIN_CS = 7,
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DI_PIN_SER_CLK = 0,
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DI_PIN_SER_RS = 1,
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};
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enum di_sync_wave {
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DI_SYNC_NONE = -1,
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DI_SYNC_CLK = 0,
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DI_SYNC_INT_HSYNC = 1,
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DI_SYNC_HSYNC = 2,
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DI_SYNC_VSYNC = 3,
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DI_SYNC_DE = 5,
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};
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struct ipu_cm {
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u32 conf;
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u32 sisg_ctrl0;
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u32 sisg_ctrl1;
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u32 sisg_set[6];
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u32 sisg_clear[6];
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u32 int_ctrl[15];
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u32 sdma_event[10];
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u32 srm_pri1;
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u32 srm_pri2;
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u32 fs_proc_flow[3];
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u32 fs_disp_flow[2];
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u32 skip;
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u32 disp_alt_conf;
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u32 disp_gen;
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u32 disp_alt[4];
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u32 snoop;
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u32 mem_rst;
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u32 pm;
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u32 gpr;
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u32 reserved0[26];
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u32 ch_db_mode_sel[2];
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u32 reserved1[4];
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u32 alt_ch_db_mode_sel[2];
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u32 reserved2[2];
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u32 ch_trb_mode_sel[2];
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};
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struct ipu_idmac {
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u32 conf;
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u32 ch_en[2];
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u32 sep_alpha;
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u32 alt_sep_alpha;
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u32 ch_pri[2];
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u32 wm_en[2];
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u32 lock_en[2];
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u32 sub_addr[5];
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u32 bndm_en[2];
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u32 sc_cord[2];
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u32 reserved[44];
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u32 ch_busy[2];
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};
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struct ipu_com_async {
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u32 com_conf_async;
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u32 graph_wind_ctrl_async;
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u32 fg_pos_async;
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u32 cur_pos_async;
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u32 cur_map_async;
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u32 gamma_c_async[8];
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u32 gamma_s_async[4];
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u32 dp_csca_async[4];
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u32 dp_csc_async[2];
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};
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struct ipu_dp {
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u32 com_conf_sync;
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u32 graph_wind_ctrl_sync;
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u32 fg_pos_sync;
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u32 cur_pos_sync;
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u32 cur_map_sync;
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u32 gamma_c_sync[8];
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u32 gamma_s_sync[4];
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u32 csca_sync[4];
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u32 csc_sync[2];
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u32 cur_pos_alt;
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struct ipu_com_async async[2];
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};
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struct ipu_di {
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u32 general;
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u32 bs_clkgen0;
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u32 bs_clkgen1;
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u32 sw_gen0[9];
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u32 sw_gen1[9];
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u32 sync_as;
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u32 dw_gen[12];
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u32 dw_set[48];
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u32 stp_rep[4];
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u32 stp_rep9;
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u32 ser_conf;
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u32 ssc;
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u32 pol;
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u32 aw0;
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u32 aw1;
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u32 scr_conf;
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u32 stat;
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};
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struct ipu_stat {
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u32 int_stat[15];
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u32 cur_buf[2];
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u32 alt_cur_buf_0;
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u32 alt_cur_buf_1;
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u32 srm_stat;
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u32 proc_task_stat;
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u32 disp_task_stat;
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u32 triple_cur_buf[4];
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u32 ch_buf0_rdy[2];
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u32 ch_buf1_rdy[2];
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u32 alt_ch_buf0_rdy[2];
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u32 alt_ch_buf1_rdy[2];
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u32 ch_buf2_rdy[2];
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};
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struct ipu_dc_ch {
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u32 wr_ch_conf;
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u32 wr_ch_addr;
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u32 rl[5];
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};
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struct ipu_dc {
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struct ipu_dc_ch dc_ch0_1_2[3];
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u32 cmd_ch_conf_3;
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u32 cmd_ch_conf_4;
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struct ipu_dc_ch dc_ch5_6[2];
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struct ipu_dc_ch dc_ch8;
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u32 rl6_ch_8;
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struct ipu_dc_ch dc_ch9;
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u32 rl6_ch_9;
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u32 gen;
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u32 disp_conf1[4];
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u32 disp_conf2[4];
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u32 di0_conf[2];
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u32 di1_conf[2];
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u32 dc_map_ptr[15];
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u32 dc_map_val[12];
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u32 udge[16];
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u32 lla[2];
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u32 r_lla[2];
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u32 wr_ch_addr_5_alt;
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u32 stat;
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};
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struct ipu_dmfc {
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u32 rd_chan;
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u32 wr_chan;
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u32 wr_chan_def;
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u32 dp_chan;
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u32 dp_chan_def;
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u32 general[2];
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u32 ic_ctrl;
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u32 wr_chan_alt;
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u32 wr_chan_def_alt;
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u32 general1_alt;
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u32 stat;
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};
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#define IPU_CM_REG ((struct ipu_cm *)(IPU_CTRL_BASE_ADDR + \
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IPU_CM_REG_BASE))
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#define IPU_CONF (&IPU_CM_REG->conf)
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#define IPU_SRM_PRI1 (&IPU_CM_REG->srm_pri1)
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#define IPU_SRM_PRI2 (&IPU_CM_REG->srm_pri2)
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#define IPU_FS_PROC_FLOW1 (&IPU_CM_REG->fs_proc_flow[0])
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#define IPU_FS_PROC_FLOW2 (&IPU_CM_REG->fs_proc_flow[1])
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#define IPU_FS_PROC_FLOW3 (&IPU_CM_REG->fs_proc_flow[2])
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#define IPU_FS_DISP_FLOW1 (&IPU_CM_REG->fs_disp_flow[0])
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#define IPU_DISP_GEN (&IPU_CM_REG->disp_gen)
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#define IPU_MEM_RST (&IPU_CM_REG->mem_rst)
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#define IPU_GPR (&IPU_CM_REG->gpr)
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#define IPU_CHA_DB_MODE_SEL(ch) (&IPU_CM_REG->ch_db_mode_sel[ch / 32])
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#define IPU_STAT ((struct ipu_stat *)(IPU_CTRL_BASE_ADDR + \
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IPU_STAT_REG_BASE))
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#define IPU_INT_STAT(n) (&IPU_STAT->int_stat[(n) - 1])
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#define IPU_CHA_CUR_BUF(ch) (&IPU_STAT->cur_buf[ch / 32])
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#define IPU_CHA_BUF0_RDY(ch) (&IPU_STAT->ch_buf0_rdy[ch / 32])
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#define IPU_CHA_BUF1_RDY(ch) (&IPU_STAT->ch_buf1_rdy[ch / 32])
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#define IPUIRQ_2_STATREG(irq) (IPU_INT_STAT(1) + ((irq) / 32))
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#define IPUIRQ_2_MASK(irq) (1UL << ((irq) & 0x1F))
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#define IPU_INT_CTRL(n) (&IPU_CM_REG->int_ctrl[(n) - 1])
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#define IDMAC_REG ((struct ipu_idmac *)(IPU_CTRL_BASE_ADDR + \
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IPU_IDMAC_REG_BASE))
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#define IDMAC_CONF (&IDMAC_REG->conf)
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#define IDMAC_CHA_EN(ch) (&IDMAC_REG->ch_en[ch / 32])
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#define IDMAC_CHA_PRI(ch) (&IDMAC_REG->ch_pri[ch / 32])
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#define DI_REG(di) ((struct ipu_di *)(IPU_CTRL_BASE_ADDR + \
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((di == 1) ? IPU_DI1_REG_BASE : \
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IPU_DI0_REG_BASE)))
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#define DI_GENERAL(di) (&DI_REG(di)->general)
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#define DI_BS_CLKGEN0(di) (&DI_REG(di)->bs_clkgen0)
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#define DI_BS_CLKGEN1(di) (&DI_REG(di)->bs_clkgen1)
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#define DI_SW_GEN0(di, gen) (&DI_REG(di)->sw_gen0[gen - 1])
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#define DI_SW_GEN1(di, gen) (&DI_REG(di)->sw_gen1[gen - 1])
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#define DI_STP_REP(di, gen) (&DI_REG(di)->stp_rep[(gen - 1) / 2])
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#define DI_STP_REP9(di) (&DI_REG(di)->stp_rep9)
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#define DI_SYNC_AS_GEN(di) (&DI_REG(di)->sync_as)
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#define DI_DW_GEN(di, gen) (&DI_REG(di)->dw_gen[gen])
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#define DI_DW_SET(di, gen, set) (&DI_REG(di)->dw_set[gen + 12 * set])
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#define DI_POL(di) (&DI_REG(di)->pol)
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#define DI_SCR_CONF(di) (&DI_REG(di)->scr_conf)
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#define DMFC_REG ((struct ipu_dmfc *)(IPU_CTRL_BASE_ADDR + \
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IPU_DMFC_REG_BASE))
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#define DMFC_WR_CHAN (&DMFC_REG->wr_chan)
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#define DMFC_WR_CHAN_DEF (&DMFC_REG->wr_chan_def)
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#define DMFC_DP_CHAN (&DMFC_REG->dp_chan)
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#define DMFC_DP_CHAN_DEF (&DMFC_REG->dp_chan_def)
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#define DMFC_GENERAL1 (&DMFC_REG->general[0])
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#define DMFC_IC_CTRL (&DMFC_REG->ic_ctrl)
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#define DC_REG ((struct ipu_dc *)(IPU_CTRL_BASE_ADDR + \
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IPU_DC_REG_BASE))
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#define DC_MAP_CONF_PTR(n) (&DC_REG->dc_map_ptr[n / 2])
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#define DC_MAP_CONF_VAL(n) (&DC_REG->dc_map_val[n / 2])
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static inline struct ipu_dc_ch *dc_ch_offset(int ch)
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{
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switch (ch) {
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case 0:
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case 1:
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case 2:
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return &DC_REG->dc_ch0_1_2[ch];
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case 5:
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case 6:
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return &DC_REG->dc_ch5_6[ch - 5];
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case 8:
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return &DC_REG->dc_ch8;
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case 9:
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return &DC_REG->dc_ch9;
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default:
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printf("%s: invalid channel %d\n", __func__, ch);
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return NULL;
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}
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}
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#define DC_RL_CH(ch, evt) (&dc_ch_offset(ch)->rl[evt / 2])
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#define DC_WR_CH_CONF(ch) (&dc_ch_offset(ch)->wr_ch_conf)
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#define DC_WR_CH_ADDR(ch) (&dc_ch_offset(ch)->wr_ch_addr)
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#define DC_WR_CH_CONF_1 DC_WR_CH_CONF(1)
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#define DC_WR_CH_CONF_5 DC_WR_CH_CONF(5)
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#define DC_GEN (&DC_REG->gen)
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#define DC_DISP_CONF2(disp) (&DC_REG->disp_conf2[disp])
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#define DC_STAT (&DC_REG->stat)
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#define DP_SYNC 0
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#define DP_ASYNC0 0x60
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#define DP_ASYNC1 0xBC
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#define DP_REG ((struct ipu_dp *)(IPU_CTRL_BASE_ADDR + \
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IPU_DP_REG_BASE))
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#define DP_COM_CONF() (&DP_REG->com_conf_sync)
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#define DP_GRAPH_WIND_CTRL() (&DP_REG->graph_wind_ctrl_sync)
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#define DP_CSC_A_0() (&DP_REG->csca_sync[0])
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#define DP_CSC_A_1() (&DP_REG->csca_sync[1])
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#define DP_CSC_A_2() (&DP_REG->csca_sync[2])
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#define DP_CSC_A_3() (&DP_REG->csca_sync[3])
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#define DP_CSC_0() (&DP_REG->csc_sync[0])
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#define DP_CSC_1() (&DP_REG->csc_sync[1])
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/* DC template opcodes */
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#define WROD(lf) (0x18 | (lf << 1))
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#endif
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