upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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98 lines
2.9 KiB
98 lines
2.9 KiB
/*
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* Copyright 2007 Freescale Semiconductor, Inc.
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* York Sun <yorksun@freescale.com>
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*
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* FSL DIU Framebuffer driver
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/io.h>
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#include <fsl_diu_fb.h>
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void diu_set_pixel_clock(unsigned int pixclock)
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{
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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volatile ccsr_gur_t *gur = &immap->im_gur;
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volatile unsigned int *guts_clkdvdr = &gur->clkdvdr;
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unsigned long speed_ccb, temp, pixval;
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speed_ccb = get_bus_freq(0);
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temp = 1000000000/pixclock;
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temp *= 1000;
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pixval = speed_ccb / temp;
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debug("DIU pixval = %lu\n", pixval);
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/* Modify PXCLK in GUTS CLKDVDR */
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debug("DIU: Current value of CLKDVDR = 0x%08x\n", *guts_clkdvdr);
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temp = *guts_clkdvdr & 0x2000FFFF;
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*guts_clkdvdr = temp; /* turn off clock */
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*guts_clkdvdr = temp | 0x80000000 | ((pixval & 0x1F) << 16);
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debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *guts_clkdvdr);
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}
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int platform_diu_init(unsigned int *xres, unsigned int *yres)
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{
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char *monitor_port;
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int gamma_fix;
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unsigned int pixel_format;
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unsigned char tmp_val;
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unsigned char pixis_arch;
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u8 *pixis_base = (u8 *)PIXIS_BASE;
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tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
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pixis_arch = in_8(pixis_base + PIXIS_VER);
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monitor_port = getenv("monitor");
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if (!strncmp(monitor_port, "0", 1)) { /* 0 - DVI */
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*xres = 1280;
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*yres = 1024;
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if (pixis_arch == 0x01)
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pixel_format = 0x88882317;
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else
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pixel_format = 0x88883316;
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gamma_fix = 0;
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out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x08);
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} else if (!strncmp(monitor_port, "1", 1)) { /* 1 - Single link LVDS */
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*xres = 1024;
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*yres = 768;
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pixel_format = 0x88883316;
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gamma_fix = 0;
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out_8(pixis_base + PIXIS_BRDCFG0, (tmp_val & 0xf7) | 0x10);
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} else if (!strncmp(monitor_port, "2", 1)) { /* 2 - Double link LVDS */
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*xres = 1280;
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*yres = 1024;
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pixel_format = 0x88883316;
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gamma_fix = 1;
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out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xe7);
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} else { /* DVI */
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*xres = 1280;
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*yres = 1024;
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pixel_format = 0x88882317;
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gamma_fix = 0;
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out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x08);
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}
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return fsl_diu_init(*xres, pixel_format, gamma_fix);
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}
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