upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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55 lines
2.1 KiB
55 lines
2.1 KiB
/*
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* (C) Copyright 2010,2011
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* NVIDIA Corporation <www.nvidia.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _PINMUX_H_
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#define _PINMUX_H_
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/* APB MISC Pin Mux and Tristate (APB_MISC_PP_) registers */
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struct pmux_tri_ctlr {
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uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */
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uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */
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uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */
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uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */
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uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */
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uint pmt_tri_a; /* _TRI_STATE_REG_A_0, offset 14 */
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uint pmt_tri_b; /* _TRI_STATE_REG_B_0, offset 18 */
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uint pmt_tri_c; /* _TRI_STATE_REG_C_0, offset 1C */
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uint pmt_tri_d; /* _TRI_STATE_REG_D_0, offset 20 */
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uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */
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uint pmt_reserved[22]; /* ABP_MISC_PP_ reserved offs 28-7C */
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uint pmt_ctl_a; /* _PIN_MUX_CTL_A_0, offset 80 */
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uint pmt_ctl_b; /* _PIN_MUX_CTL_B_0, offset 84 */
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uint pmt_ctl_c; /* _PIN_MUX_CTL_C_0, offset 88 */
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uint pmt_ctl_d; /* _PIN_MUX_CTL_D_0, offset 8C */
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uint pmt_ctl_e; /* _PIN_MUX_CTL_E_0, offset 90 */
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uint pmt_ctl_f; /* _PIN_MUX_CTL_F_0, offset 94 */
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uint pmt_ctl_g; /* _PIN_MUX_CTL_G_0, offset 98 */
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};
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#define Z_GMC (1 << 29)
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#define Z_IRRX (1 << 20)
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#define Z_IRTX (1 << 19)
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#endif /* PINMUX_H */
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