upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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451 lines
12 KiB
451 lines
12 KiB
/*
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* Copyright (C) 2005 Sandburst Corporation
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <common.h>
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#include <command.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <spd_sdram.h>
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#include <i2c.h>
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#include "ppc440gx_i2c.h"
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#include "sb_common.h"
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DECLARE_GLOBAL_DATA_PTR;
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long int fixed_sdram (void);
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/*************************************************************************
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* metrobox_get_master
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*
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* PRI_N - active low signal. If the GPIO pin is low we are the master
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*
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************************************************************************/
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int sbcommon_get_master(void)
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{
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ppc440_gpio_regs_t *gpio_regs;
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gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE;
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if (gpio_regs->in & SBCOMMON_GPIO_PRI_N) {
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return 0;
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}
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else {
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return 1;
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}
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}
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/*************************************************************************
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* metrobox_secondary_present
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*
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* Figure out if secondary/slave board is present
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*
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************************************************************************/
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int sbcommon_secondary_present(void)
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{
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ppc440_gpio_regs_t *gpio_regs;
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gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE;
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if (gpio_regs->in & SBCOMMON_GPIO_SEC_PRES)
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return 0;
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else
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return 1;
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}
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/*************************************************************************
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* sbcommon_get_serial_number
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*
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* Retrieve the board serial number via the mac address in eeprom
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*
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************************************************************************/
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unsigned short sbcommon_get_serial_number(void)
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{
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unsigned char buff[0x100];
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unsigned short sernum;
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/* Get the board serial number from eeprom */
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/* Initialize I2C */
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i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
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/* Read 256 bytes in EEPROM */
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i2c_read (0x50, 0, 1, buff, 0x100);
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memcpy(&sernum, &buff[0xF4], 2);
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sernum /= 32;
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return (sernum);
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}
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/*************************************************************************
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* sbcommon_fans
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*
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* Spin up fans 2 & 3 to get some air moving. OS will take care
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* of the rest. This is mostly a precaution...
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*
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* Assumes i2c bus 1 is ready.
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*
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************************************************************************/
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void sbcommon_fans(void)
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{
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/*
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* Attempt to turn on 2 of the fans...
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* Need to go through the bridge
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*/
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puts ("FANS: ");
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/* select fan4 through the bridge */
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i2c_reg_write1(0x73, /* addr */
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0x00, /* reg */
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0x08); /* val = bus 4 */
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/* Turn on FAN 4 */
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i2c_reg_write1(0x2e,
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1,
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0x80);
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i2c_reg_write1(0x2e,
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0,
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0x19);
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/* Deselect bus 4 on the bridge */
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i2c_reg_write1(0x73,
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0x00,
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0x00);
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/* select fan3 through the bridge */
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i2c_reg_write1(0x73, /* addr */
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0x00, /* reg */
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0x04); /* val = bus 3 */
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/* Turn on FAN 3 */
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i2c_reg_write1(0x2e,
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1,
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0x80);
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i2c_reg_write1(0x2e,
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0,
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0x19);
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/* Deselect bus 3 on the bridge */
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i2c_reg_write1(0x73,
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0x00,
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0x00);
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/* select fan2 through the bridge */
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i2c_reg_write1(0x73, /* addr */
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0x00, /* reg */
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0x02); /* val = bus 4 */
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/* Turn on FAN 2 */
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i2c_reg_write1(0x2e,
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1,
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0x80);
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i2c_reg_write1(0x2e,
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0,
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0x19);
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/* Deselect bus 2 on the bridge */
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i2c_reg_write1(0x73,
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0x00,
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0x00);
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/* select fan1 through the bridge */
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i2c_reg_write1(0x73, /* addr */
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0x00, /* reg */
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0x01); /* val = bus 0 */
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/* Turn on FAN 1 */
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i2c_reg_write1(0x2e,
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1,
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0x80);
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i2c_reg_write1(0x2e,
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0,
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0x19);
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/* Deselect bus 1 on the bridge */
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i2c_reg_write1(0x73,
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0x00,
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0x00);
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puts ("on\n");
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return;
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}
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/*************************************************************************
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* initdram
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*
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* Initialize sdram
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*
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************************************************************************/
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long int initdram (int board_type)
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{
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long dram_size = 0;
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#if defined(CONFIG_SPD_EEPROM)
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dram_size = spd_sdram ();
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#else
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dram_size = fixed_sdram ();
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#endif
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return dram_size;
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}
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/*************************************************************************
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* testdram
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*
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*
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************************************************************************/
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#if defined(CFG_DRAM_TEST)
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int testdram (void)
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{
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uint *pstart = (uint *) CFG_MEMTEST_START;
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uint *pend = (uint *) CFG_MEMTEST_END;
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uint *p;
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printf("Testing SDRAM: ");
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for (p = pstart; p < pend; p++)
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*p = 0xaaaaaaaa;
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for (p = pstart; p < pend; p++) {
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if (*p != 0xaaaaaaaa) {
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printf ("SDRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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for (p = pstart; p < pend; p++)
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*p = 0x55555555;
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for (p = pstart; p < pend; p++) {
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if (*p != 0x55555555) {
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printf ("SDRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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printf("OK\n");
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return 0;
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}
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#endif
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#if !defined(CONFIG_SPD_EEPROM)
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/*************************************************************************
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* fixed sdram init -- doesn't use serial presence detect.
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*
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* Assumes: 128 MB, non-ECC, non-registered
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* PLB @ 133 MHz
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*
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************************************************************************/
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long int fixed_sdram (void)
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{
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uint reg;
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/*--------------------------------------------------------------------
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* Setup some default
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*------------------------------------------------------------------*/
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mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */
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mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
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mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
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mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
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mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
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/*--------------------------------------------------------------------
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* Setup for board-specific specific mem
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*------------------------------------------------------------------*/
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/*
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* Following for CAS Latency = 2.5 @ 133 MHz PLB
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*/
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mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
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mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
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/* RA=10 RD=3 */
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mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
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mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
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mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
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udelay (400); /* Delay 200 usecs (min) */
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/*--------------------------------------------------------------------
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* Enable the controller, then wait for DCEN to complete
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*------------------------------------------------------------------*/
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mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
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for (;;) {
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mfsdram (mem_mcsts, reg);
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if (reg & 0x80000000)
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break;
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}
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return (128 * 1024 * 1024); /* 128 MB */
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}
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#endif /* !defined(CONFIG_SPD_EEPROM) */
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/*************************************************************************
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* pci_pre_init
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*
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* This routine is called just prior to registering the hose and gives
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* the board the opportunity to check things. Returning a value of zero
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* indicates that things are bad & PCI initialization should be aborted.
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*
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* Different boards may wish to customize the pci controller structure
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* (add regions, override default access routines, etc) or perform
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* certain pre-initialization actions.
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*
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************************************************************************/
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#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
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int pci_pre_init(struct pci_controller * hose )
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{
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unsigned long strap;
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/*--------------------------------------------------------------------------+
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* The metrobox is always configured as the host & requires the
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* PCI arbiter to be enabled.
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*--------------------------------------------------------------------------*/
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mfsdr(sdr_sdstp1, strap);
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if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
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printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
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return 0;
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}
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return 1;
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}
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#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
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/*************************************************************************
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* pci_target_init
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*
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* The bootstrap configuration provides default settings for the pci
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* inbound map (PIM). But the bootstrap config choices are limited and
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* may not be sufficient for a given board.
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*
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************************************************************************/
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#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
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void pci_target_init(struct pci_controller * hose )
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{
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/*--------------------------------------------------------------------------+
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* Disable everything
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*--------------------------------------------------------------------------*/
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out32r( PCIX0_PIM0SA, 0 ); /* disable */
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out32r( PCIX0_PIM1SA, 0 ); /* disable */
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out32r( PCIX0_PIM2SA, 0 ); /* disable */
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out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
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/*--------------------------------------------------------------------------+
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* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
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* options to not support sizes such as 128/256 MB.
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*--------------------------------------------------------------------------*/
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out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
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out32r( PCIX0_PIM0LAH, 0 );
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out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
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out32r( PCIX0_BAR0, 0 );
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/*--------------------------------------------------------------------------+
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* Program the board's subsystem id/vendor id
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*--------------------------------------------------------------------------*/
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out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
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out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
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out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
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}
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#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
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/*************************************************************************
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* is_pci_host
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*
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*
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************************************************************************/
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#if defined(CONFIG_PCI)
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int is_pci_host(struct pci_controller *hose)
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{
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/* The metrobox is always configured as host. */
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return(1);
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}
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#endif /* defined(CONFIG_PCI) */
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/*************************************************************************
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* board_get_enetaddr
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*
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* Get the ethernet MAC address for the management ethernet from the
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* strap EEPROM. Note that is the BASE address for the range of
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* external ethernet MACs on the board. The base + 31 is the actual
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* mgmt mac address.
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*
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************************************************************************/
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static int macaddr_idx = 0;
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void board_get_enetaddr (uchar * enet)
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{
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int i;
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unsigned short tmp;
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unsigned char buff[0x100], *cp;
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if (0 == macaddr_idx) {
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/* Initialize I2C */
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i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
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/* Read 256 bytes in EEPROM */
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i2c_read (0x50, 0, 1, buff, 0x100);
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cp = &buff[0xF0];
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for (i = 0; i < 6; i++,cp++)
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enet[i] = *cp;
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memcpy(&tmp, &enet[4], 2);
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tmp += 31;
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memcpy(&enet[4], &tmp, 2);
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macaddr_idx++;
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} else {
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enet[0] = 0x02;
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enet[1] = 0x00;
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enet[2] = 0x00;
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enet[3] = 0x00;
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enet[4] = 0x00;
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if (1 == sbcommon_get_master() ) {
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/* Master/Primary card */
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enet[5] = 0x01;
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} else {
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/* Slave/Secondary card */
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enet [5] = 0x02;
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}
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}
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return;
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}
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#ifdef CONFIG_POST
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/*
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* Returns 1 if keys pressed to start the power-on long-running tests
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* Called from board_init_f().
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*/
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int post_hotkeys_pressed(void)
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{
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return (ctrlc());
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}
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#endif
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