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785 lines
31 KiB
785 lines
31 KiB
/**
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* @file IxParityENAcc.h
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*
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* @author Intel Corporation
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* @date 24 Mar 2004
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*
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* @brief This file contains the public API for the IXP400 Parity Error
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* Notifier access component.
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*
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* @par
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* IXP400 SW Release version 2.0
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*
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* -- Copyright Notice --
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*
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* @par
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* Copyright 2001-2005, Intel Corporation.
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* All rights reserved.
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*
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* @par
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Intel Corporation nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @par
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* -- End of Copyright Notice --
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*/
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/**
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* @defgroup IxParityENAcc IXP400 Parity Error Notifier (IxParityENAcc) API
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*
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* @brief The public API for the Parity Error Notifier
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*
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* @{
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*/
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#ifndef IXPARITYENACC_H
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#define IXPARITYENACC_H
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#ifdef __ixp46X
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#include "IxOsal.h"
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/*
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* #defines for function return types, etc.
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*/
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/**
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* @ingroup IxParityENAcc
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*
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* @enum IxParityENAccStatus
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*
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* @brief The status as returend from the API
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*/
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typedef enum /**< IxParityENAccStatus */
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{
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IX_PARITYENACC_SUCCESS = IX_SUCCESS, /**< The request is successful */
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IX_PARITYENACC_INVALID_PARAMETERS, /**< Invalid or NULL parameters passed */
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IX_PARITYENACC_NOT_INITIALISED, /**< Access layer has not been initialised before accessing the APIs */
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IX_PARITYENACC_ALREADY_INITIALISED, /**< Access layer has already been initialised */
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IX_PARITYENACC_OPERATION_FAILED, /**< Operation did not succeed due to hardware failure */
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IX_PARITYENACC_NO_PARITY /**< No parity condition exits or has already been cleared */
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} IxParityENAccStatus;
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/**
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* @ingroup IxParityENAcc
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*
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* @enum IxParityENAccParityType
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*
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* @brief Odd or Even Parity Type
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*/
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typedef enum /**< IxParityENAccParityType */
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{
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IX_PARITYENACC_EVEN_PARITY, /**< Even Parity */
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IX_PARITYENACC_ODD_PARITY /**< Odd Parity */
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} IxParityENAccParityType;
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/**
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* @ingroup IxParityENAcc
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*
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* @enum IxParityENAccConfigOption
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*
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* @brief The parity error enable/disable configuration option
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*/
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typedef enum /**< IxParityENAccConfigOption */
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{
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IX_PARITYENACC_DISABLE, /**< Disable parity error detection */
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IX_PARITYENACC_ENABLE /**< Enable parity error detection */
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} IxParityENAccConfigOption;
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/**
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* @ingroup IxParityENAcc
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*
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* @struct IxParityENAccNpeConfig
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*
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* @brief NPE parity detection is to be enabled/disabled
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*/
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typedef struct /**< IxParityENAccNpeConfig */
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{
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IxParityENAccConfigOption ideEnabled; /**< NPE IMem, DMem and External */
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IxParityENAccParityType parityOddEven; /**< Parity - Odd or Even */
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} IxParityENAccNpeConfig ;
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/**
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* @ingroup IxParityENAcc
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*
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* @struct IxParityENAccMcuConfig
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*
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* @brief MCU pairty detection is to be enabled/disabled
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*/
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typedef struct /**< IxParityENAccMcuConfig */
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{
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IxParityENAccConfigOption singlebitDetectEnabled; /**< Single-bit parity error detection */
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IxParityENAccConfigOption singlebitCorrectionEnabled; /**< Single-bit parity error correction */
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IxParityENAccConfigOption multibitDetectionEnabled; /**< Multi-bit parity error detection */
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} IxParityENAccMcuConfig ;
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/**
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* @ingroup IxParityENAcc
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*
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* @struct IxParityENAccEbcConfig
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*
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* @brief Expansion Bus Controller parity detection is to be enabled or disabled
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*
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* Note: All the Chip Select(s) and External Masters will have the same parity
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*/
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typedef struct /**< IxParityENAccEbcConfig */
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{
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IxParityENAccConfigOption ebcCs0Enabled; /**< Expansion Bus Controller - Chip Select 0 */
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IxParityENAccConfigOption ebcCs1Enabled; /**< Expansion Bus Controller - Chip Select 1 */
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IxParityENAccConfigOption ebcCs2Enabled; /**< Expansion Bus Controller - Chip Select 2 */
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IxParityENAccConfigOption ebcCs3Enabled; /**< Expansion Bus Controller - Chip Select 3 */
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IxParityENAccConfigOption ebcCs4Enabled; /**< Expansion Bus Controller - Chip Select 4 */
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IxParityENAccConfigOption ebcCs5Enabled; /**< Expansion Bus Controller - Chip Select 5 */
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IxParityENAccConfigOption ebcCs6Enabled; /**< Expansion Bus Controller - Chip Select 6 */
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IxParityENAccConfigOption ebcCs7Enabled; /**< Expansion Bus Controller - Chip Select 7 */
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IxParityENAccConfigOption ebcExtMstEnabled; /**< External Master on Expansion bus */
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IxParityENAccParityType parityOddEven; /**< Parity - Odd or Even */
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} IxParityENAccEbcConfig ;
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/**
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* @ingroup IxParityENAcc
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*
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* @struct IxParityENAccHWParityConfig
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*
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* @brief Parity error configuration of the Hardware Blocks
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*/
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typedef struct /**< IxParityENAccHWParityConfig */
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{
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IxParityENAccNpeConfig npeAConfig; /**< NPE A parity detection is to be enabled/disabled */
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IxParityENAccNpeConfig npeBConfig; /**< NPE B parity detection is to be enabled/disabled */
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IxParityENAccNpeConfig npeCConfig; /**< NPE C parity detection is to be enabled/disabled */
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IxParityENAccMcuConfig mcuConfig; /**< MCU pairty detection is to be enabled/disabled */
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IxParityENAccConfigOption swcpEnabled; /**< SWCP parity detection is to be enabled */
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IxParityENAccConfigOption aqmEnabled; /**< AQM parity detection is to be enabled */
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IxParityENAccEbcConfig ebcConfig; /**< Expansion Bus Controller parity detection is to be enabled/disabled */
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} IxParityENAccHWParityConfig;
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/**
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* @ingroup IxParityENAcc
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*
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* @struct IxParityENAccNpeParityErrorStats
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*
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* @brief NPE parity error statistics
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*/
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typedef struct /* IxParityENAccNpeParityErrorStats */
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{
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UINT32 parityErrorsIMem; /**< Parity errors in Instruction Memory */
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UINT32 parityErrorsDMem; /**< Parity errors in Data Memory */
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UINT32 parityErrorsExternal; /**< Parity errors in NPE External Entities */
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} IxParityENAccNpeParityErrorStats;
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/**
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* @ingroup IxParityENAcc
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*
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* @struct IxParityENAccMcuParityErrorStats
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*
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* @brief DDR Memory Control Unit parity error statistics
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*
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* Note: There could be two outstanding parity errors at any given time whose address
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* details captured. If there is no room for the new interrupt then it would be treated
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* as overflow parity condition.
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*/
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typedef struct /* IxParityENAccMcuParityErrorStats */
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{
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UINT32 parityErrorsSingleBit; /**< Parity errors of the type Single-Bit */
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UINT32 parityErrorsMultiBit; /**< Parity errors of the type Multi-Bit */
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UINT32 parityErrorsOverflow; /**< Parity errors when more than two parity errors occured */
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} IxParityENAccMcuParityErrorStats;
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/**
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* @ingroup IxParityENAcc
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*
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* @struct IxParityENAccEbcParityErrorStats
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*
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* @brief Expansion Bus Controller parity error statistics
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*/
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typedef struct /* IxParityENAccEbcParityErrorStats */
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{
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UINT32 parityErrorsInbound; /**< Odd bit parity errors on inbound transfers */
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UINT32 parityErrorsOutbound; /**< Odd bit parity errors on outbound transfers */
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} IxParityENAccEbcParityErrorStats;
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/**
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* @ingroup IxParityENAcc
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*
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* @struct IxParityENAccParityErrorStats
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*
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* @brief Parity Error Statistics for the all the hardware blocks
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*/
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typedef struct /**< IxParityENAccParityErrorStats */
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{
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IxParityENAccNpeParityErrorStats npeStats; /**< NPE parity error statistics */
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IxParityENAccMcuParityErrorStats mcuStats; /**< MCU parity error statistics */
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IxParityENAccEbcParityErrorStats ebcStats; /**< EBC parity error statistics */
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UINT32 swcpStats; /**< SWCP parity error statistics */
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UINT32 aqmStats; /**< AQM parity error statistics */
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} IxParityENAccParityErrorStats;
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/**
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* @ingroup IxParityENAcc
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*
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* @enum IxParityENAccParityErrorSource
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*
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* @brief The source of the parity error notification
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*/
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typedef enum /**< IxParityENAccParityErrorSource */
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{
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IX_PARITYENACC_NPE_A_IMEM, /**< NPE A - Instruction memory */
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IX_PARITYENACC_NPE_A_DMEM, /**< NPE A - Data memory */
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IX_PARITYENACC_NPE_A_EXT, /**< NPE A - External Entity*/
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IX_PARITYENACC_NPE_B_IMEM, /**< NPE B - Instruction memory */
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IX_PARITYENACC_NPE_B_DMEM, /**< NPE B - Data memory */
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IX_PARITYENACC_NPE_B_EXT, /**< NPE B - External Entity*/
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IX_PARITYENACC_NPE_C_IMEM, /**< NPE C - Instruction memory */
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IX_PARITYENACC_NPE_C_DMEM, /**< NPE C - Data memory */
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IX_PARITYENACC_NPE_C_EXT, /**< NPE C - External Entity*/
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IX_PARITYENACC_SWCP, /**< SWCP */
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IX_PARITYENACC_AQM, /**< AQM */
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IX_PARITYENACC_MCU_SBIT, /**< DDR Memory Controller Unit - Single bit parity */
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IX_PARITYENACC_MCU_MBIT, /**< DDR Memory Controller Unit - Multi bit parity */
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IX_PARITYENACC_MCU_OVERFLOW, /**< DDR Memory Controller Unit - Parity errors in excess of two */
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IX_PARITYENACC_EBC_CS, /**< Expansion Bus Controller - Chip Select */
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IX_PARITYENACC_EBC_EXTMST /**< Expansion Bus Controller - External Master */
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} IxParityENAccParityErrorSource;
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/**
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* @ingroup IxParityENAcc
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*
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* @enum IxParityENAccParityErrorAccess
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*
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* @brief The type of access resulting in parity error
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*/
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typedef enum /**< IxParityENAccParityErrorAccess */
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{
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IX_PARITYENACC_READ, /**< Read Access */
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IX_PARITYENACC_WRITE /**< Write Access */
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} IxParityENAccParityErrorAccess;
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/**
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* @ingroup IxParityENAcc
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*
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* @typedef IxParityENAccParityErrorAddress
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*
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* @brief The memory location which has parity error
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*/
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typedef UINT32 IxParityENAccParityErrorAddress;
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/**
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* @ingroup IxParityENAcc
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*
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* @typedef IxParityENAccParityErrorData
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*
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* @brief The data read from the memory location which has parity error
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*/
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typedef UINT32 IxParityENAccParityErrorData;
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/**
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* @ingroup IxParityENAcc
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*
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* @enum IxParityENAccParityErrorRequester
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*
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* @brief The requester interface through which the SDRAM memory access
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* resulted in the parity error.
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*/
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typedef enum /**< IxParityENAccParityErrorRequester */
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{
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IX_PARITYENACC_MPI, /**< Direct Memory Port Interface */
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IX_PARITYENACC_AHB_BUS /**< South or North AHB Bus */
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} IxParityENAccParityErrorRequester;
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/**
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* @ingroup IxParityENAcc
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*
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* @enum IxParityENAccAHBErrorMaster
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*
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* @brief The Master on the AHB bus interface whose transaction might have
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* resulted in the parity error notification to XScale.
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*/
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typedef enum /**< IxParityENAccAHBErrorMaster */
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{
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IX_PARITYENACC_AHBN_MST_NPE_A, /**< NPE - A */
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IX_PARITYENACC_AHBN_MST_NPE_B, /**< NPE - B */
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IX_PARITYENACC_AHBN_MST_NPE_C, /**< NPE - C */
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IX_PARITYENACC_AHBS_MST_XSCALE, /**< XScale Bus Interface Unit */
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IX_PARITYENACC_AHBS_MST_PBC, /**< PCI Bus Controller */
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IX_PARITYENACC_AHBS_MST_EBC, /**< Expansion Bus Controller */
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IX_PARITYENACC_AHBS_MST_AHB_BRIDGE, /**< AHB Bridge */
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IX_PARITYENACC_AHBS_MST_USBH /**< USB Host Controller */
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} IxParityENAccAHBErrorMaster;
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/**
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* @ingroup IxParityENAcc
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*
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* @enum IxParityENAccAHBErrorSlave
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*
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* @brief The Slave on the AHB bus interface whose transaction might have
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* resulted in the parity error notification to XScale.
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*/
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typedef enum /**< IxParityENAccAHBErrorSlave */
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{
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IX_PARITYENACC_AHBN_SLV_MCU, /**< Memory Control Unit */
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IX_PARITYENACC_AHBN_SLV_AHB_BRIDGE, /**< AHB Bridge */
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IX_PARITYENACC_AHBS_SLV_MCU, /**< XScale Bus Interface Unit */
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IX_PARITYENACC_AHBS_SLV_APB_BRIDGE, /**< APB Bridge */
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IX_PARITYENACC_AHBS_SLV_AQM, /**< AQM */
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IX_PARITYENACC_AHBS_SLV_RSA, /**< RSA (Crypto Bus) */
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IX_PARITYENACC_AHBS_SLV_PBC, /**< PCI Bus Controller */
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IX_PARITYENACC_AHBS_SLV_EBC, /**< Expansion Bus Controller */
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IX_PARITYENACC_AHBS_SLV_USBH /**< USB Host Controller */
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} IxParityENAccAHBErrorSlave;
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/**
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* @ingroup IxParityENAcc
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*
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* @struct IxParityENAccAHBErrorTransaction
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*
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* @brief The Master and Slave on the AHB bus interface whose transaction might
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* have resulted in the parity error notification to XScale.
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*
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* NOTE: This information may be used in the data abort exception handler
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* to differentiate between the XScale and non-XScale access to the SDRAM
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* memory.
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*/
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typedef struct /**< IxParityENAccAHBErrorTransaction */
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{
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IxParityENAccAHBErrorMaster ahbErrorMaster; /**< Master on AHB bus */
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IxParityENAccAHBErrorSlave ahbErrorSlave; /**< Slave on AHB bus */
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} IxParityENAccAHBErrorTransaction;
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/**
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* @ingroup IxParityENAcc
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*
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* @struct IxParityENAccParityErrorContextMessage
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*
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* @brief Parity Error Context Message
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*/
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typedef struct /**< IxParityENAccParityErrorContextMessage */
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{
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IxParityENAccParityErrorSource pecParitySource; /**< Source info of parity error */
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IxParityENAccParityErrorAccess pecAccessType; /**< Read or Write Access
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Read - NPE, SWCP, AQM, DDR MCU,
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Exp Bus Ctrlr (Outbound)
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Write - DDR MCU,
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Exp Bus Ctrlr (Inbound
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i.e., External Master) */
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IxParityENAccParityErrorAddress pecAddress; /**< Address faulty location
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Valid only for AQM, DDR MCU,
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Exp Bus Ctrlr */
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IxParityENAccParityErrorData pecData; /**< Data read from the faulty location
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Valid only for AQM and DDR MCU
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For DDR MCU it is the bit location
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of the Single-bit parity */
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IxParityENAccParityErrorRequester pecRequester; /**< Requester of SDRAM memory access
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Valid only for the DDR MCU */
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IxParityENAccAHBErrorTransaction ahbErrorTran; /**< Master and Slave information on the
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last AHB Error Transaction */
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} IxParityENAccParityErrorContextMessage;
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/**
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* @ingroup IxParityENAcc
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*
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* @typedef IxParityENAccCallback
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*
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* @brief This prototype shows the format of a callback function.
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*
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* The callback will be used to notify the parity error to the client application.
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* The callback will be registered by @ref ixParityENAccCallbackRegister.
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*
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* It will be called from an ISR when a parity error is detected and thus
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* needs to follow the interrupt callable function conventions.
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*
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*/
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typedef void (*IxParityENAccCallback) (void);
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/*
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* Prototypes for interface functions.
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*/
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/**
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* @ingroup IxParityENAcc
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*
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* @fn IxParityENAccStatus ixParityENAccInit(void)
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*
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* @brief This function will initialise the IxParityENAcc component.
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*
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* This function will initialise the IxParityENAcc component. It should only be
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* called once, prior to using the IxParityENAcc component.
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*
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* <OL><LI>It initialises the internal data structures, registers the ISR that
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* will be triggered when a parity error occurs in IXP4xx silicon.</LI></OL>
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*
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* @li Re-entrant : No
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* @li ISR Callable : No
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*
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* @return @li IX_PARITYENACC_SUCCESS - Initialization is successful
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* @li IX_PARITYENACC_ALREADY_INITIALISED - The access layer has already
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* been initialized
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* @li IX_PARITYENACC_OPERATION_FAILED - The request failed because the
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* operation didn't succeed on the hardware. Refer to error trace/log
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* for details.
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*/
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PUBLIC IxParityENAccStatus ixParityENAccInit(void);
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/**
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* @ingroup IxParityENAcc
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*
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* @fn IxParityENAccStatus ixParityENAccCallbackRegister (
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IxParityENAccCallback parityErrNfyCallBack)
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*
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* @brief This function will register a new callback with IxParityENAcc component.
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* It can also reregister a new callback replacing the old callback.
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*
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* @param parityErrNfyCallBack [in] - This parameter will specify the call-back
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|
* function supplied by the client application.
|
|
*
|
|
* This interface registers the user application supplied call-back handler with
|
|
* the parity error handling access component after the init.
|
|
*
|
|
* The callback function will be called from an ISR that will be triggered by the
|
|
* parity error in the IXP400 silicon.
|
|
*
|
|
* The following actions will be performed by this function:
|
|
* <OL><LI>Check for the prior initialisation of the module before registering or
|
|
* re-registering of the callback.
|
|
* Check for parity error detection disabled before re-registration of the callback.
|
|
* </LI></OL>
|
|
*
|
|
* @li Re-entrant : No
|
|
* @li ISR Callable : No
|
|
*
|
|
* @return @li IX_PARITYENACC_SUCCESS - The parameters check passed and the
|
|
* registration is successful.
|
|
* @li IX_PARITYENACC_INVALID_PARAMETERS - Request failed due to NULL
|
|
* parameter passed.
|
|
* @li IX_PARITYENACC_OPERATION_FAILED - The request failed because the
|
|
* parity error detection not yet disabled.
|
|
* @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior to
|
|
* the initialisation of the access layer.
|
|
*/
|
|
|
|
PUBLIC IxParityENAccStatus ixParityENAccCallbackRegister (
|
|
IxParityENAccCallback parityErrNfyCallBack);
|
|
|
|
/**
|
|
* @ingroup IxParityENAcc
|
|
*
|
|
* @fn IxParityENAccStatus ixParityENAccParityDetectionConfigure (
|
|
const IxParityENAccHWParityConfig *hwParityConfig)
|
|
*
|
|
* @brief This interface allows the client application to enable the parity
|
|
* error detection on the underlying hardware block.
|
|
*
|
|
* @param hwParityConfig [in] - Hardware blocks for which the parity error
|
|
* detection is to be enabled or disabled.
|
|
*
|
|
* The client application allocates and provides the reference to the buffer.
|
|
*
|
|
* It will also verify whether the specific hardware block is functional or not.
|
|
*
|
|
* NOTE: Failure in enabling or disabling of one or more components result in
|
|
* trace message but still returns IX_PARITYENACC_SUCCESS. Refer to the function
|
|
* @ref ixParityENAccParityDetectionQuery on how to verify the failures while
|
|
* enabling/disabling paritys error detection.
|
|
*
|
|
* It shall be invoked after the Init and CallbackRegister functions but before
|
|
* any other function of the IxParityENAcc layer.
|
|
*
|
|
* @li Re-entrant : No
|
|
* @li ISR Callable : No
|
|
*
|
|
* @return @li IX_PARITYENACC_SUCCESS - The parameters check passed and the
|
|
* request to enable/disable is successful.
|
|
* @li IX_PARITYENACC_INVALID_PARAMETERS-The request failed due to
|
|
* NULL parameter supplied.
|
|
* @li IX_PARITYENACC_OPERATION_FAILED - The request failed because the
|
|
* operation didn't succeed on the hardware.
|
|
* @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior to
|
|
* the initialisation of the access layer.
|
|
*/
|
|
|
|
PUBLIC IxParityENAccStatus ixParityENAccParityDetectionConfigure (
|
|
const IxParityENAccHWParityConfig *hwParityConfig);
|
|
|
|
/**
|
|
* @ingroup IxParityENAcc
|
|
*
|
|
* @fn IxParityENAccStatus ixParityENAccParityDetectionQuery (
|
|
IxParityENAccHWParityConfig * const hwParityConfig)
|
|
*
|
|
* @brief This interface allows the client application to determine the
|
|
* status of the parity error detection on the specified hardware blocks
|
|
*
|
|
* @param hwParityConfig [out] - Hardware blocks whose parity error detection
|
|
* has been enabled or disabled.
|
|
*
|
|
* The client application allocates and provides the reference to the buffer.
|
|
*
|
|
* This interface can be used immediately after the interface @ref
|
|
* ixParityENAccParityDetectionConfigure to see on which of the hardware blocks
|
|
* the parity error detection has either been enabled or disabled based on the
|
|
* client application request.
|
|
*
|
|
* @li Re-entrant : No
|
|
* @li ISR Callable : No
|
|
*
|
|
* @return @li IX_PARITYENACC_SUCCESS - The parameters check passed and the
|
|
* request to query on whether the hardware parity error detection
|
|
* is enabled or disabled is successful.
|
|
* @li IX_PARITYENACC_INVALID_PARAMETERS-The request failed due to
|
|
* NULL parameter or invalid values supplied.
|
|
* @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior
|
|
* to the initialisation of the access layer.
|
|
*/
|
|
|
|
PUBLIC IxParityENAccStatus ixParityENAccParityDetectionQuery(
|
|
IxParityENAccHWParityConfig * const hwParityConfig);
|
|
|
|
/**
|
|
* @ingroup IxParityENAcc
|
|
*
|
|
* @fn IxParityENAccStatus ixParityENAccParityErrorContextGet(
|
|
IxParityENAccParityErrorContextMessage * const pecMessage)
|
|
*
|
|
* @brief This interface allows the client application to determine the
|
|
* status of the parity error context on hardware block for which the
|
|
* current parity error interrupt triggered.
|
|
*
|
|
* @param pecMessage [out] - The parity error context information of the
|
|
* parity interrupt currently being process.
|
|
*
|
|
* The client application allocates and provides the reference to the buffer.
|
|
*
|
|
* Refer to the data structure @ref IxParityENAccParityErrorContextMessage
|
|
* for details.
|
|
*
|
|
* The routine will will fetch the parity error context in the following
|
|
* priority, if multiple parity errors observed.
|
|
*
|
|
* <pre>
|
|
* 0 - MCU (Multi-bit and single-bit in that order)
|
|
* 1 - NPE-A
|
|
* 2 - NPE-B
|
|
* 3 - NPE-C
|
|
* 4 - SWCP
|
|
* 5 - QM
|
|
* 6 - EXP
|
|
*
|
|
* NOTE: The information provided in the @ref IxParityENAccAHBErrorTransaction
|
|
* may be of help for the client application to decide on the course of action
|
|
* to take. This info is taken from the Performance Monitoring Unit register
|
|
* which records most recent error observed on the AHB bus. This information
|
|
* might have been overwritten by some other error by the time it is retrieved.
|
|
* </pre>
|
|
*
|
|
* @li Re-entrant : No
|
|
* @li ISR Callable : Yes
|
|
*
|
|
* @return @li IX_PARITYENACC_SUCCESS-The parameters check passed and the
|
|
* request to get the parity error context information is successful.
|
|
* @li IX_PARITYENACC_INVALID_PARAMETERS-The request failed due to
|
|
* NULL parameter is passed
|
|
* @li IX_PARITYENACC_OPERATION_FAILED - The request failed because
|
|
* the operation didn't succeed on the hardware.
|
|
* @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior
|
|
* to the initialisation of the access layer.
|
|
* @li IX_PARITYENACC_NO_PARITY - No parity condition exits or has
|
|
* already been cleared
|
|
*/
|
|
|
|
PUBLIC IxParityENAccStatus ixParityENAccParityErrorContextGet(
|
|
IxParityENAccParityErrorContextMessage * const pecMessage);
|
|
|
|
/**
|
|
* @ingroup IxParityENAcc
|
|
*
|
|
* @fn IxParityENAccStatus ixParityENAccParityErrorInterruptClear (
|
|
const IxParityENAccParityErrorContextMessage *pecMessage)
|
|
*
|
|
* @brief This interface helps the client application to clear off the
|
|
* interrupt condition on the hardware block identified in the parity
|
|
* error context message. Please refer to the table below as the operation
|
|
* varies depending on the interrupt source.
|
|
*
|
|
* @param pecMessage [in] - The parity error context information of the
|
|
* hardware block whose parity error interrupt condition is to disabled.
|
|
*
|
|
* The client application allocates and provides the reference to the buffer.
|
|
*
|
|
* <pre>
|
|
* ****************************************************************************
|
|
* Following actions will be taken during the interrupt clear for respective
|
|
* hardware blocks.
|
|
*
|
|
* Parity Source Actions taken during Interrupt clear
|
|
* ------------- -------------------------------------------------------
|
|
* NPE-A Interrupt will be masked off at the interrupt controller
|
|
* so that it will not trigger continuously.
|
|
* Client application has to take appropriate action and
|
|
* re-configure the parity error detection subsequently.
|
|
* The client application will not be notified of further
|
|
* interrupts, until the re-configuration is done using
|
|
* @ref ixParityENAccParityDetectionConfigure.
|
|
*
|
|
* NPE-B Interrupt will be masked off at the interrupt controller
|
|
* so that it will not trigger continuously.
|
|
* Client application has to take appropriate action and
|
|
* re-configure the parity error detection subsequently.
|
|
* The client application will not be notified of further
|
|
* interrupts, until the re-configuration is done using
|
|
* @ref ixParityENAccParityDetectionConfigure.
|
|
*
|
|
* NPE-C Interrupt will be masked off at the interrupt controller
|
|
* Client application has to take appropriate action and
|
|
* re-configure the parity error detection subsequently.
|
|
* The client application will not be notified of further
|
|
* interrupts, until the re-configuration is done using
|
|
* @ref ixParityENAccParityDetectionConfigure.
|
|
*
|
|
* SWCP Interrupt will be masked off at the interrupt controller.
|
|
* Client application has to take appropriate action and
|
|
* re-configure the parity error detection subsequently.
|
|
* The client application will not be notified of further
|
|
* interrupts, until the re-configuration is done using
|
|
* @ref ixParityENAccParityDetectionConfigure.
|
|
*
|
|
* AQM Interrupt will be masked off at the interrupt controller.
|
|
* Client application has to take appropriate action and
|
|
* re-configure the parity error detection subsequently.
|
|
* The client application will not be notified of further
|
|
* interrupts, until the re-configuration is done using
|
|
* @ref ixParityENAccParityDetectionConfigure.
|
|
*
|
|
* MCU Parity interrupt condition is cleared at the SDRAM MCU for
|
|
* the following:
|
|
* 1. Single-bit
|
|
* 2. Multi-bit
|
|
* 3. Overflow condition i.e., more than two parity conditions
|
|
* occurred
|
|
* Note that single-parity errors do not result in data abort
|
|
* and not all data aborts caused by multi-bit parity error.
|
|
*
|
|
* EXP Parity interrupt condition is cleared at the expansion bus
|
|
* controller for the following:
|
|
* 1. External master initiated Inbound write
|
|
* 2. Internal master (IXP400) initiated Outbound read
|
|
* ****************************************************************************
|
|
* </pre>
|
|
* @li Re-entrant : No
|
|
* @li ISR Callable : No
|
|
*
|
|
* @return @li IX_PARITYENACC_SUCCESS-The parameters check passed and the request
|
|
* to clear the parity error interrupt condition is successful.
|
|
* @li IX_PARITYENACC_INVALID_PARAMETERS-The request failed due to
|
|
* NULL parameters have been passed or contents have been
|
|
* supplied with invalid values.
|
|
* @li IX_PARITYENACC_OPERATION_FAILED - The request failed because
|
|
* the operation didn't succeed on the hardware.
|
|
* @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior
|
|
* to the initialisation of the access layer.
|
|
*/
|
|
|
|
PUBLIC IxParityENAccStatus ixParityENAccParityErrorInterruptClear (
|
|
const IxParityENAccParityErrorContextMessage *pecMessage);
|
|
|
|
/**
|
|
* @ingroup IxParityENAcc
|
|
*
|
|
* @fn IxParityENAccStatus ixParityENAccStatsGet (
|
|
IxParityENAccParityErrorStats * const ixParityErrorStats)
|
|
*
|
|
* @brief This interface allows the client application to retrieve parity
|
|
* error statistics for all the hardware blocks
|
|
*
|
|
* @param ixParityErrorStats - [out] The statistics for all the hardware blocks.
|
|
*
|
|
* The client application allocates and provides the reference to the buffer.
|
|
*
|
|
* @li Re-entrant : No
|
|
* @li ISR Callable : Yes
|
|
*
|
|
* @return @li IX_PARITYENACC_SUCCESS-The parameters check passed and the
|
|
* request to retrieve parity error statistics for the hardware
|
|
* block is successful.
|
|
* @li IX_PARITYENACC_INVALID_PARAMETERS-The request failed due to a
|
|
* NULL parameter passed.
|
|
* @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior
|
|
* to the initialisation of the access layer.
|
|
*/
|
|
|
|
PUBLIC IxParityENAccStatus ixParityENAccStatsGet (
|
|
IxParityENAccParityErrorStats * const ixParityErrorStats);
|
|
|
|
/**
|
|
* @ingroup IxParityENAcc
|
|
*
|
|
* @fn IxParityENAccStatus ixParityENAccStatsShow (void)
|
|
*
|
|
* @brief This interface allows the client application to print all the
|
|
* parity error statistics.
|
|
*
|
|
* @li Re-entrant : No
|
|
* @li ISR Callable : No
|
|
*
|
|
* @return @li IX_PARITYENACC_SUCCESS - The request to show the pairty
|
|
* error statistics is successful.
|
|
* @li IX_PARITYENACC_NOT_INITIALISED - The operation requested
|
|
* prior to the initialisation of the access layer.
|
|
*/
|
|
|
|
PUBLIC IxParityENAccStatus ixParityENAccStatsShow (void);
|
|
|
|
/**
|
|
* @ingroup IxParityENAcc
|
|
*
|
|
* @fn IxParityENAccStatus ixParityENAccStatsReset (void)
|
|
*
|
|
* @brief This interface allows the client application to reset all the
|
|
* parity error statistics.
|
|
*
|
|
* @li Re-entrant : No
|
|
* @li ISR Callable : No
|
|
*
|
|
* @return @li IX_PARITYENACC_SUCCESS - The request to reset the parity
|
|
* error statistics is successful.
|
|
* @li IX_PARITYENACC_NOT_INITIALISED - The operation requested
|
|
* prior to the initialisation of the access layer.
|
|
*/
|
|
|
|
PUBLIC IxParityENAccStatus ixParityENAccStatsReset (void);
|
|
|
|
#endif /* IXPARITYENACC_H */
|
|
#endif /* __ixp46X */
|
|
|
|
/**
|
|
* @} defgroup IxParityENAcc
|
|
*/
|
|
|
|
|