upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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1192 lines
34 KiB
1192 lines
34 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2013
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* Lokesh Vutla <lokeshvutla@ti.com>
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*
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* Based on previous work by:
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* Aneesh V <aneesh@ti.com>
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* Steve Sakoman <steve@sakoman.com>
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*/
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#include <common.h>
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#include <palmas.h>
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#include <sata.h>
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#include <linux/string.h>
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#include <asm/gpio.h>
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#include <usb.h>
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#include <linux/usb/gadget.h>
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#include <asm/omap_common.h>
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#include <asm/omap_sec_common.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/dra7xx_iodelay.h>
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#include <asm/emif.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/sata.h>
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#include <environment.h>
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#include <dwc3-uboot.h>
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#include <dwc3-omap-uboot.h>
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#include <ti-usb-phy-uboot.h>
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#include <miiphy.h>
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#include "mux_data.h"
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#include "../common/board_detect.h"
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#define board_is_dra76x_evm() board_ti_is("DRA76/7x")
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#define board_is_dra74x_evm() board_ti_is("5777xCPU")
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#define board_is_dra72x_evm() board_ti_is("DRA72x-T")
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#define board_is_dra71x_evm() board_ti_is("DRA79x,D")
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#define board_is_dra74x_revh_or_later() (board_is_dra74x_evm() && \
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(strncmp("H", board_ti_get_rev(), 1) <= 0))
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#define board_is_dra72x_revc_or_later() (board_is_dra72x_evm() && \
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(strncmp("C", board_ti_get_rev(), 1) <= 0))
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#define board_ti_get_emif_size() board_ti_get_emif1_size() + \
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board_ti_get_emif2_size()
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#ifdef CONFIG_DRIVER_TI_CPSW
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#include <cpsw.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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/* GPIO 7_11 */
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#define GPIO_DDR_VTT_EN 203
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#define SYSINFO_BOARD_NAME_MAX_LEN 37
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const struct omap_sysinfo sysinfo = {
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"Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n"
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};
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static const struct emif_regs emif1_ddr3_532_mhz_1cs = {
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.sdram_config_init = 0x61851ab2,
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.sdram_config = 0x61851ab2,
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.sdram_config2 = 0x08000000,
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.ref_ctrl = 0x000040F1,
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.ref_ctrl_final = 0x00001035,
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.sdram_tim1 = 0xCCCF36B3,
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.sdram_tim2 = 0x308F7FDA,
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.sdram_tim3 = 0x427F88A8,
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.read_idle_ctrl = 0x00050000,
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.zq_config = 0x0007190B,
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.temp_alert_config = 0x00000000,
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.emif_ddr_phy_ctlr_1_init = 0x0024400B,
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.emif_ddr_phy_ctlr_1 = 0x0E24400B,
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.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
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.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
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.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
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.emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
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.emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
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.emif_rd_wr_lvl_rmp_win = 0x00000000,
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.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
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.emif_rd_wr_lvl_ctl = 0x00000000,
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.emif_rd_wr_exec_thresh = 0x00000305
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};
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static const struct emif_regs emif2_ddr3_532_mhz_1cs = {
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.sdram_config_init = 0x61851B32,
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.sdram_config = 0x61851B32,
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.sdram_config2 = 0x08000000,
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.ref_ctrl = 0x000040F1,
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.ref_ctrl_final = 0x00001035,
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.sdram_tim1 = 0xCCCF36B3,
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.sdram_tim2 = 0x308F7FDA,
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.sdram_tim3 = 0x427F88A8,
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.read_idle_ctrl = 0x00050000,
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.zq_config = 0x0007190B,
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.temp_alert_config = 0x00000000,
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.emif_ddr_phy_ctlr_1_init = 0x0024400B,
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.emif_ddr_phy_ctlr_1 = 0x0E24400B,
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.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
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.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
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.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
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.emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
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.emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
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.emif_rd_wr_lvl_rmp_win = 0x00000000,
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.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
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.emif_rd_wr_lvl_ctl = 0x00000000,
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.emif_rd_wr_exec_thresh = 0x00000305
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};
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static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
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.sdram_config_init = 0x61862B32,
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.sdram_config = 0x61862B32,
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.sdram_config2 = 0x08000000,
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.ref_ctrl = 0x0000514C,
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.ref_ctrl_final = 0x0000144A,
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.sdram_tim1 = 0xD113781C,
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.sdram_tim2 = 0x30717FE3,
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.sdram_tim3 = 0x409F86A8,
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.read_idle_ctrl = 0x00050000,
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.zq_config = 0x5007190B,
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.temp_alert_config = 0x00000000,
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.emif_ddr_phy_ctlr_1_init = 0x0024400D,
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.emif_ddr_phy_ctlr_1 = 0x0E24400D,
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.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
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.emif_ddr_ext_phy_ctrl_2 = 0x00A400A4,
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.emif_ddr_ext_phy_ctrl_3 = 0x00A900A9,
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.emif_ddr_ext_phy_ctrl_4 = 0x00B000B0,
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.emif_ddr_ext_phy_ctrl_5 = 0x00B000B0,
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.emif_rd_wr_lvl_rmp_win = 0x00000000,
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.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
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.emif_rd_wr_lvl_ctl = 0x00000000,
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.emif_rd_wr_exec_thresh = 0x00000305
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};
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const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = {
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.sdram_config_init = 0x61862BB2,
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.sdram_config = 0x61862BB2,
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.sdram_config2 = 0x00000000,
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.ref_ctrl = 0x0000514D,
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.ref_ctrl_final = 0x0000144A,
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.sdram_tim1 = 0xD1137824,
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.sdram_tim2 = 0x30B37FE3,
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.sdram_tim3 = 0x409F8AD8,
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.read_idle_ctrl = 0x00050000,
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.zq_config = 0x5007190B,
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.temp_alert_config = 0x00000000,
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.emif_ddr_phy_ctlr_1_init = 0x0824400E,
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.emif_ddr_phy_ctlr_1 = 0x0E24400E,
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.emif_ddr_ext_phy_ctrl_1 = 0x04040100,
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.emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
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.emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
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.emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
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.emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
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.emif_rd_wr_lvl_rmp_win = 0x00000000,
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.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
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.emif_rd_wr_lvl_ctl = 0x00000000,
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.emif_rd_wr_exec_thresh = 0x00000305
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};
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const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = {
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.sdram_config_init = 0x61851ab2,
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.sdram_config = 0x61851ab2,
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.sdram_config2 = 0x08000000,
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.ref_ctrl = 0x000040F1,
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.ref_ctrl_final = 0x00001035,
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.sdram_tim1 = 0xCCCF36B3,
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.sdram_tim2 = 0x30BF7FDA,
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.sdram_tim3 = 0x427F8BA8,
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.read_idle_ctrl = 0x00050000,
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.zq_config = 0x0007190B,
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.temp_alert_config = 0x00000000,
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.emif_ddr_phy_ctlr_1_init = 0x0024400B,
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.emif_ddr_phy_ctlr_1 = 0x0E24400B,
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.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
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.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
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.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
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.emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
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.emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
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.emif_rd_wr_lvl_rmp_win = 0x00000000,
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.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
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.emif_rd_wr_lvl_ctl = 0x00000000,
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.emif_rd_wr_exec_thresh = 0x00000305
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};
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const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = {
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.sdram_config_init = 0x61851B32,
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.sdram_config = 0x61851B32,
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.sdram_config2 = 0x08000000,
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.ref_ctrl = 0x000040F1,
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.ref_ctrl_final = 0x00001035,
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.sdram_tim1 = 0xCCCF36B3,
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.sdram_tim2 = 0x308F7FDA,
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.sdram_tim3 = 0x427F88A8,
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.read_idle_ctrl = 0x00050000,
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.zq_config = 0x0007190B,
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.temp_alert_config = 0x00000000,
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.emif_ddr_phy_ctlr_1_init = 0x0024400B,
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.emif_ddr_phy_ctlr_1 = 0x0E24400B,
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.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
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.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
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.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
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.emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
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.emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
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.emif_rd_wr_lvl_rmp_win = 0x00000000,
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.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
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.emif_rd_wr_lvl_ctl = 0x00000000,
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.emif_rd_wr_exec_thresh = 0x00000305
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};
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const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra76 = {
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.sdram_config_init = 0x61862B32,
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.sdram_config = 0x61862B32,
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.sdram_config2 = 0x00000000,
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.ref_ctrl = 0x0000514C,
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.ref_ctrl_final = 0x0000144A,
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.sdram_tim1 = 0xD113783C,
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.sdram_tim2 = 0x30B47FE3,
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.sdram_tim3 = 0x409F8AD8,
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.read_idle_ctrl = 0x00050000,
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.zq_config = 0x5007190B,
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.temp_alert_config = 0x00000000,
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.emif_ddr_phy_ctlr_1_init = 0x0824400D,
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.emif_ddr_phy_ctlr_1 = 0x0E24400D,
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.emif_ddr_ext_phy_ctrl_1 = 0x04040100,
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.emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
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.emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
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.emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
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.emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
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.emif_rd_wr_lvl_rmp_win = 0x00000000,
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.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
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.emif_rd_wr_lvl_ctl = 0x00000000,
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.emif_rd_wr_exec_thresh = 0x00000305
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};
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const struct emif_regs emif_2_regs_ddr3_666_mhz_1cs_dra76 = {
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.sdram_config_init = 0x61862B32,
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.sdram_config = 0x61862B32,
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.sdram_config2 = 0x00000000,
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.ref_ctrl = 0x0000514C,
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.ref_ctrl_final = 0x0000144A,
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.sdram_tim1 = 0xD113781C,
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.sdram_tim2 = 0x30B47FE3,
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.sdram_tim3 = 0x409F8AD8,
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.read_idle_ctrl = 0x00050000,
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.zq_config = 0x5007190B,
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.temp_alert_config = 0x00000000,
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.emif_ddr_phy_ctlr_1_init = 0x0824400D,
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.emif_ddr_phy_ctlr_1 = 0x0E24400D,
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.emif_ddr_ext_phy_ctrl_1 = 0x04040100,
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.emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
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.emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
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.emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
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.emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
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.emif_rd_wr_lvl_rmp_win = 0x00000000,
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.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
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.emif_rd_wr_lvl_ctl = 0x00000000,
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.emif_rd_wr_exec_thresh = 0x00000305
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};
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void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
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{
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u64 ram_size;
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ram_size = board_ti_get_emif_size();
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switch (omap_revision()) {
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case DRA752_ES1_0:
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case DRA752_ES1_1:
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case DRA752_ES2_0:
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switch (emif_nr) {
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case 1:
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if (ram_size > CONFIG_MAX_MEM_MAPPED)
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*regs = &emif1_ddr3_532_mhz_1cs_2G;
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else
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*regs = &emif1_ddr3_532_mhz_1cs;
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break;
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case 2:
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if (ram_size > CONFIG_MAX_MEM_MAPPED)
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*regs = &emif2_ddr3_532_mhz_1cs_2G;
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else
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*regs = &emif2_ddr3_532_mhz_1cs;
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break;
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}
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break;
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case DRA762_ABZ_ES1_0:
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case DRA762_ACD_ES1_0:
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case DRA762_ES1_0:
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if (emif_nr == 1)
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*regs = &emif_1_regs_ddr3_666_mhz_1cs_dra76;
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else
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*regs = &emif_2_regs_ddr3_666_mhz_1cs_dra76;
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break;
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case DRA722_ES1_0:
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case DRA722_ES2_0:
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case DRA722_ES2_1:
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if (ram_size < CONFIG_MAX_MEM_MAPPED)
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*regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
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else
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*regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2;
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break;
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default:
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*regs = &emif1_ddr3_532_mhz_1cs;
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}
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}
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static const struct dmm_lisa_map_regs lisa_map_dra7_1536MB = {
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.dmm_lisa_map_0 = 0x0,
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.dmm_lisa_map_1 = 0x80640300,
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.dmm_lisa_map_2 = 0xC0500220,
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.dmm_lisa_map_3 = 0xFF020100,
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.is_ma_present = 0x1
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};
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static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
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.dmm_lisa_map_0 = 0x0,
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.dmm_lisa_map_1 = 0x0,
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.dmm_lisa_map_2 = 0x80600100,
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.dmm_lisa_map_3 = 0xFF020100,
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.is_ma_present = 0x1
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};
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const struct dmm_lisa_map_regs lisa_map_dra7_2GB = {
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.dmm_lisa_map_0 = 0x0,
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.dmm_lisa_map_1 = 0x0,
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.dmm_lisa_map_2 = 0x80740300,
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.dmm_lisa_map_3 = 0xFF020100,
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.is_ma_present = 0x1
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};
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|
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/*
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* DRA722 EVM EMIF1 2GB CONFIGURATION
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* EMIF1 4 devices of 512Mb x 8 Micron
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*/
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const struct dmm_lisa_map_regs lisa_map_2G_x_4 = {
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.dmm_lisa_map_0 = 0x0,
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.dmm_lisa_map_1 = 0x0,
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.dmm_lisa_map_2 = 0x80700100,
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.dmm_lisa_map_3 = 0xFF020100,
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.is_ma_present = 0x1
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};
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void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
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{
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u64 ram_size;
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ram_size = board_ti_get_emif_size();
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switch (omap_revision()) {
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case DRA762_ABZ_ES1_0:
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case DRA762_ACD_ES1_0:
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case DRA762_ES1_0:
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case DRA752_ES1_0:
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case DRA752_ES1_1:
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case DRA752_ES2_0:
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if (ram_size > CONFIG_MAX_MEM_MAPPED)
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*dmm_lisa_regs = &lisa_map_dra7_2GB;
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else
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*dmm_lisa_regs = &lisa_map_dra7_1536MB;
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break;
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case DRA722_ES1_0:
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case DRA722_ES2_0:
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case DRA722_ES2_1:
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default:
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if (ram_size < CONFIG_MAX_MEM_MAPPED)
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*dmm_lisa_regs = &lisa_map_2G_x_2;
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else
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*dmm_lisa_regs = &lisa_map_2G_x_4;
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break;
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}
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}
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struct vcores_data dra752_volts = {
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.mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
|
|
.mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
|
|
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
|
|
.mpu.addr = TPS659038_REG_ADDR_SMPS12,
|
|
.mpu.pmic = &tps659038,
|
|
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
|
|
|
|
.eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
|
|
.eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
|
|
.eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
|
|
.eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
|
|
.eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
|
|
.eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
|
|
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
|
|
.eve.addr = TPS659038_REG_ADDR_SMPS45,
|
|
.eve.pmic = &tps659038,
|
|
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
|
|
|
|
.gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
|
|
.gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
|
|
.gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
|
|
.gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
|
|
.gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
|
|
.gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
|
|
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
|
|
.gpu.addr = TPS659038_REG_ADDR_SMPS6,
|
|
.gpu.pmic = &tps659038,
|
|
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
|
|
|
|
.core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
|
|
.core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
|
|
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
|
|
.core.addr = TPS659038_REG_ADDR_SMPS7,
|
|
.core.pmic = &tps659038,
|
|
|
|
.iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
|
|
.iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
|
|
.iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
|
|
.iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
|
|
.iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
|
|
.iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
|
|
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
|
|
.iva.addr = TPS659038_REG_ADDR_SMPS8,
|
|
.iva.pmic = &tps659038,
|
|
.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
|
|
};
|
|
|
|
struct vcores_data dra76x_volts = {
|
|
.mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
|
|
.mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
|
|
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
|
|
.mpu.addr = LP87565_REG_ADDR_BUCK01,
|
|
.mpu.pmic = &lp87565,
|
|
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
|
|
|
|
.eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
|
|
.eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
|
|
.eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
|
|
.eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
|
|
.eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
|
|
.eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
|
|
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
|
|
.eve.addr = TPS65917_REG_ADDR_SMPS1,
|
|
.eve.pmic = &tps659038,
|
|
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
|
|
|
|
.gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
|
|
.gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
|
|
.gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
|
|
.gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
|
|
.gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
|
|
.gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
|
|
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
|
|
.gpu.addr = LP87565_REG_ADDR_BUCK23,
|
|
.gpu.pmic = &lp87565,
|
|
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
|
|
|
|
.core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
|
|
.core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
|
|
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
|
|
.core.addr = TPS65917_REG_ADDR_SMPS3,
|
|
.core.pmic = &tps659038,
|
|
|
|
.iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
|
|
.iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
|
|
.iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
|
|
.iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
|
|
.iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
|
|
.iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
|
|
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
|
|
.iva.addr = TPS65917_REG_ADDR_SMPS4,
|
|
.iva.pmic = &tps659038,
|
|
.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
|
|
};
|
|
|
|
struct vcores_data dra722_volts = {
|
|
.mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
|
|
.mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
|
|
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
|
|
.mpu.addr = TPS65917_REG_ADDR_SMPS1,
|
|
.mpu.pmic = &tps659038,
|
|
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
|
|
|
|
.core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
|
|
.core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
|
|
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
|
|
.core.addr = TPS65917_REG_ADDR_SMPS2,
|
|
.core.pmic = &tps659038,
|
|
|
|
/*
|
|
* The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
|
|
* designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
|
|
*/
|
|
.gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
|
|
.gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
|
|
.gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
|
|
.gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
|
|
.gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
|
|
.gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
|
|
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
|
|
.gpu.addr = TPS65917_REG_ADDR_SMPS3,
|
|
.gpu.pmic = &tps659038,
|
|
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
|
|
|
|
.eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
|
|
.eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
|
|
.eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
|
|
.eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
|
|
.eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
|
|
.eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
|
|
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
|
|
.eve.addr = TPS65917_REG_ADDR_SMPS3,
|
|
.eve.pmic = &tps659038,
|
|
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
|
|
|
|
.iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
|
|
.iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
|
|
.iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
|
|
.iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
|
|
.iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
|
|
.iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
|
|
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
|
|
.iva.addr = TPS65917_REG_ADDR_SMPS3,
|
|
.iva.pmic = &tps659038,
|
|
.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
|
|
};
|
|
|
|
struct vcores_data dra718_volts = {
|
|
/*
|
|
* In the case of dra71x GPU MPU and CORE
|
|
* are all powered up by BUCK0 of LP873X PMIC
|
|
*/
|
|
.mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
|
|
.mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
|
|
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
|
|
.mpu.addr = LP873X_REG_ADDR_BUCK0,
|
|
.mpu.pmic = &lp8733,
|
|
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
|
|
|
|
.core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
|
|
.core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
|
|
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
|
|
.core.addr = LP873X_REG_ADDR_BUCK0,
|
|
.core.pmic = &lp8733,
|
|
|
|
.gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
|
|
.gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
|
|
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
|
|
.gpu.addr = LP873X_REG_ADDR_BUCK0,
|
|
.gpu.pmic = &lp8733,
|
|
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
|
|
|
|
/*
|
|
* The DSPEVE and IVA rails are grouped on DRA71x-evm
|
|
* and are powered by BUCK1 of LP873X PMIC
|
|
*/
|
|
.eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
|
|
.eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
|
|
.eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
|
|
.eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
|
|
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
|
|
.eve.addr = LP873X_REG_ADDR_BUCK1,
|
|
.eve.pmic = &lp8733,
|
|
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
|
|
|
|
.iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
|
|
.iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
|
|
.iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
|
|
.iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
|
|
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
|
|
.iva.addr = LP873X_REG_ADDR_BUCK1,
|
|
.iva.pmic = &lp8733,
|
|
.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
|
|
};
|
|
|
|
int get_voltrail_opp(int rail_offset)
|
|
{
|
|
int opp;
|
|
|
|
switch (rail_offset) {
|
|
case VOLT_MPU:
|
|
opp = DRA7_MPU_OPP;
|
|
/* DRA71x supports only OPP_NOM for MPU */
|
|
if (board_is_dra71x_evm())
|
|
opp = OPP_NOM;
|
|
break;
|
|
case VOLT_CORE:
|
|
opp = DRA7_CORE_OPP;
|
|
/* DRA71x supports only OPP_NOM for CORE */
|
|
if (board_is_dra71x_evm())
|
|
opp = OPP_NOM;
|
|
break;
|
|
case VOLT_GPU:
|
|
opp = DRA7_GPU_OPP;
|
|
/* DRA71x supports only OPP_NOM for GPU */
|
|
if (board_is_dra71x_evm())
|
|
opp = OPP_NOM;
|
|
break;
|
|
case VOLT_EVE:
|
|
opp = DRA7_DSPEVE_OPP;
|
|
/*
|
|
* DRA71x does not support OPP_OD for EVE.
|
|
* If OPP_OD is selected by menuconfig, fallback
|
|
* to OPP_NOM.
|
|
*/
|
|
if (board_is_dra71x_evm() && opp == OPP_OD)
|
|
opp = OPP_NOM;
|
|
break;
|
|
case VOLT_IVA:
|
|
opp = DRA7_IVA_OPP;
|
|
/*
|
|
* DRA71x does not support OPP_OD for IVA.
|
|
* If OPP_OD is selected by menuconfig, fallback
|
|
* to OPP_NOM.
|
|
*/
|
|
if (board_is_dra71x_evm() && opp == OPP_OD)
|
|
opp = OPP_NOM;
|
|
break;
|
|
default:
|
|
opp = OPP_NOM;
|
|
}
|
|
|
|
return opp;
|
|
}
|
|
|
|
/**
|
|
* @brief board_init
|
|
*
|
|
* @return 0
|
|
*/
|
|
int board_init(void)
|
|
{
|
|
gpmc_init();
|
|
gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
|
|
|
|
return 0;
|
|
}
|
|
|
|
int dram_init_banksize(void)
|
|
{
|
|
u64 ram_size;
|
|
|
|
ram_size = board_ti_get_emif_size();
|
|
|
|
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
|
|
gd->bd->bi_dram[0].size = get_effective_memsize();
|
|
if (ram_size > CONFIG_MAX_MEM_MAPPED) {
|
|
gd->bd->bi_dram[1].start = 0x200000000;
|
|
gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int board_late_init(void)
|
|
{
|
|
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
|
char *name = "unknown";
|
|
|
|
if (is_dra72x()) {
|
|
if (board_is_dra72x_revc_or_later())
|
|
name = "dra72x-revc";
|
|
else if (board_is_dra71x_evm())
|
|
name = "dra71x";
|
|
else
|
|
name = "dra72x";
|
|
} else if (is_dra76x_abz()) {
|
|
name = "dra76x_abz";
|
|
} else if (is_dra76x_acd()) {
|
|
name = "dra76x_acd";
|
|
} else {
|
|
name = "dra7xx";
|
|
}
|
|
|
|
set_board_info_env(name);
|
|
|
|
/*
|
|
* Default FIT boot on HS devices. Non FIT images are not allowed
|
|
* on HS devices.
|
|
*/
|
|
if (get_device_type() == HS_DEVICE)
|
|
env_set("boot_fit", "1");
|
|
|
|
omap_die_id_serial();
|
|
omap_set_fastboot_vars();
|
|
|
|
/*
|
|
* Hook the LDO1 regulator to EN pin. This applies only to LP8733
|
|
* Rest all regulators are hooked to EN Pin at reset.
|
|
*/
|
|
if (board_is_dra71x_evm())
|
|
palmas_i2c_write_u8(LP873X_I2C_SLAVE_ADDR, 0x9, 0x7);
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_SPL_BUILD
|
|
void do_board_detect(void)
|
|
{
|
|
int rc;
|
|
|
|
rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
|
|
CONFIG_EEPROM_CHIP_ADDRESS);
|
|
if (rc)
|
|
printf("ti_i2c_eeprom_init failed %d\n", rc);
|
|
}
|
|
|
|
#else
|
|
|
|
void do_board_detect(void)
|
|
{
|
|
char *bname = NULL;
|
|
int rc;
|
|
|
|
rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
|
|
CONFIG_EEPROM_CHIP_ADDRESS);
|
|
if (rc)
|
|
printf("ti_i2c_eeprom_init failed %d\n", rc);
|
|
|
|
if (board_is_dra74x_evm()) {
|
|
bname = "DRA74x EVM";
|
|
} else if (board_is_dra72x_evm()) {
|
|
bname = "DRA72x EVM";
|
|
} else if (board_is_dra71x_evm()) {
|
|
bname = "DRA71x EVM";
|
|
} else if (board_is_dra76x_evm()) {
|
|
bname = "DRA76x EVM";
|
|
} else {
|
|
/* If EEPROM is not populated */
|
|
if (is_dra72x())
|
|
bname = "DRA72x EVM";
|
|
else
|
|
bname = "DRA74x EVM";
|
|
}
|
|
|
|
if (bname)
|
|
snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
|
|
"Board: %s REV %s\n", bname, board_ti_get_rev());
|
|
}
|
|
#endif /* CONFIG_SPL_BUILD */
|
|
|
|
void vcores_init(void)
|
|
{
|
|
if (board_is_dra74x_evm()) {
|
|
*omap_vcores = &dra752_volts;
|
|
} else if (board_is_dra72x_evm()) {
|
|
*omap_vcores = &dra722_volts;
|
|
} else if (board_is_dra71x_evm()) {
|
|
*omap_vcores = &dra718_volts;
|
|
} else if (board_is_dra76x_evm()) {
|
|
*omap_vcores = &dra76x_volts;
|
|
} else {
|
|
/* If EEPROM is not populated */
|
|
if (is_dra72x())
|
|
*omap_vcores = &dra722_volts;
|
|
else
|
|
*omap_vcores = &dra752_volts;
|
|
}
|
|
}
|
|
|
|
void set_muxconf_regs(void)
|
|
{
|
|
do_set_mux32((*ctrl)->control_padconf_core_base,
|
|
early_padconf, ARRAY_SIZE(early_padconf));
|
|
}
|
|
|
|
#ifdef CONFIG_IODELAY_RECALIBRATION
|
|
void recalibrate_iodelay(void)
|
|
{
|
|
struct pad_conf_entry const *pads, *delta_pads = NULL;
|
|
struct iodelay_cfg_entry const *iodelay;
|
|
int npads, niodelays, delta_npads = 0;
|
|
int ret;
|
|
|
|
switch (omap_revision()) {
|
|
case DRA722_ES1_0:
|
|
case DRA722_ES2_0:
|
|
case DRA722_ES2_1:
|
|
pads = dra72x_core_padconf_array_common;
|
|
npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
|
|
if (board_is_dra71x_evm()) {
|
|
pads = dra71x_core_padconf_array;
|
|
npads = ARRAY_SIZE(dra71x_core_padconf_array);
|
|
iodelay = dra71_iodelay_cfg_array;
|
|
niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array);
|
|
} else if (board_is_dra72x_revc_or_later()) {
|
|
delta_pads = dra72x_rgmii_padconf_array_revc;
|
|
delta_npads =
|
|
ARRAY_SIZE(dra72x_rgmii_padconf_array_revc);
|
|
iodelay = dra72_iodelay_cfg_array_revc;
|
|
niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc);
|
|
} else {
|
|
delta_pads = dra72x_rgmii_padconf_array_revb;
|
|
delta_npads =
|
|
ARRAY_SIZE(dra72x_rgmii_padconf_array_revb);
|
|
iodelay = dra72_iodelay_cfg_array_revb;
|
|
niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb);
|
|
}
|
|
break;
|
|
case DRA752_ES1_0:
|
|
case DRA752_ES1_1:
|
|
pads = dra74x_core_padconf_array;
|
|
npads = ARRAY_SIZE(dra74x_core_padconf_array);
|
|
iodelay = dra742_es1_1_iodelay_cfg_array;
|
|
niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
|
|
break;
|
|
case DRA762_ACD_ES1_0:
|
|
case DRA762_ES1_0:
|
|
pads = dra76x_core_padconf_array;
|
|
npads = ARRAY_SIZE(dra76x_core_padconf_array);
|
|
iodelay = dra76x_es1_0_iodelay_cfg_array;
|
|
niodelays = ARRAY_SIZE(dra76x_es1_0_iodelay_cfg_array);
|
|
break;
|
|
default:
|
|
case DRA752_ES2_0:
|
|
case DRA762_ABZ_ES1_0:
|
|
pads = dra74x_core_padconf_array;
|
|
npads = ARRAY_SIZE(dra74x_core_padconf_array);
|
|
iodelay = dra742_es2_0_iodelay_cfg_array;
|
|
niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
|
|
/* Setup port1 and port2 for rgmii with 'no-id' mode */
|
|
clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK |
|
|
RGMII1_ID_MODE_N_MASK);
|
|
break;
|
|
}
|
|
/* Setup I/O isolation */
|
|
ret = __recalibrate_iodelay_start();
|
|
if (ret)
|
|
goto err;
|
|
|
|
/* Do the muxing here */
|
|
do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads);
|
|
|
|
/* Now do the weird minor deltas that should be safe */
|
|
if (delta_npads)
|
|
do_set_mux32((*ctrl)->control_padconf_core_base,
|
|
delta_pads, delta_npads);
|
|
|
|
if (is_dra76x())
|
|
/* Set mux for MCAN instead of DCAN1 */
|
|
clrsetbits_le32((*ctrl)->control_core_control_spare_rw,
|
|
MCAN_SEL_ALT_MASK, MCAN_SEL);
|
|
|
|
/* Setup IOdelay configuration */
|
|
ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
|
|
err:
|
|
/* Closeup.. remove isolation */
|
|
__recalibrate_iodelay_end(ret);
|
|
}
|
|
#endif
|
|
|
|
#if defined(CONFIG_MMC)
|
|
int board_mmc_init(bd_t *bis)
|
|
{
|
|
omap_mmc_init(0, 0, 0, -1, -1);
|
|
omap_mmc_init(1, 0, 0, -1, -1);
|
|
return 0;
|
|
}
|
|
|
|
void board_mmc_poweron_ldo(uint voltage)
|
|
{
|
|
if (board_is_dra71x_evm()) {
|
|
if (voltage == LDO_VOLT_3V0)
|
|
voltage = 0x19;
|
|
else if (voltage == LDO_VOLT_1V8)
|
|
voltage = 0xa;
|
|
lp873x_mmc1_poweron_ldo(voltage);
|
|
} else if (board_is_dra76x_evm()) {
|
|
palmas_mmc1_poweron_ldo(LDO4_VOLTAGE, LDO4_CTRL, voltage);
|
|
} else {
|
|
palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage);
|
|
}
|
|
}
|
|
|
|
static const struct mmc_platform_fixups dra7x_es1_1_mmc1_fixups = {
|
|
.hw_rev = "rev11",
|
|
.unsupported_caps = MMC_CAP(MMC_HS_200) |
|
|
MMC_CAP(UHS_SDR104),
|
|
.max_freq = 96000000,
|
|
};
|
|
|
|
static const struct mmc_platform_fixups dra7x_es1_1_mmc23_fixups = {
|
|
.hw_rev = "rev11",
|
|
.unsupported_caps = MMC_CAP(MMC_HS_200) |
|
|
MMC_CAP(UHS_SDR104) |
|
|
MMC_CAP(UHS_SDR50),
|
|
.max_freq = 48000000,
|
|
};
|
|
|
|
const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
|
|
{
|
|
switch (omap_revision()) {
|
|
case DRA752_ES1_0:
|
|
case DRA752_ES1_1:
|
|
if (addr == OMAP_HSMMC1_BASE)
|
|
return &dra7x_es1_1_mmc1_fixups;
|
|
else
|
|
return &dra7x_es1_1_mmc23_fixups;
|
|
default:
|
|
return NULL;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_USB_DWC3
|
|
static struct dwc3_device usb_otg_ss1 = {
|
|
.maximum_speed = USB_SPEED_SUPER,
|
|
.base = DRA7_USB_OTG_SS1_BASE,
|
|
.tx_fifo_resize = false,
|
|
.index = 0,
|
|
};
|
|
|
|
static struct dwc3_omap_device usb_otg_ss1_glue = {
|
|
.base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
|
|
.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
|
|
.index = 0,
|
|
};
|
|
|
|
static struct ti_usb_phy_device usb_phy1_device = {
|
|
.pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
|
|
.usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
|
|
.usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
|
|
.index = 0,
|
|
};
|
|
|
|
static struct dwc3_device usb_otg_ss2 = {
|
|
.maximum_speed = USB_SPEED_SUPER,
|
|
.base = DRA7_USB_OTG_SS2_BASE,
|
|
.tx_fifo_resize = false,
|
|
.index = 1,
|
|
};
|
|
|
|
static struct dwc3_omap_device usb_otg_ss2_glue = {
|
|
.base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
|
|
.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
|
|
.index = 1,
|
|
};
|
|
|
|
static struct ti_usb_phy_device usb_phy2_device = {
|
|
.usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
|
|
.index = 1,
|
|
};
|
|
|
|
int board_usb_init(int index, enum usb_init_type init)
|
|
{
|
|
enable_usb_clocks(index);
|
|
switch (index) {
|
|
case 0:
|
|
if (init == USB_INIT_DEVICE) {
|
|
usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
|
|
usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
|
|
} else {
|
|
usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
|
|
usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
|
|
}
|
|
|
|
ti_usb_phy_uboot_init(&usb_phy1_device);
|
|
dwc3_omap_uboot_init(&usb_otg_ss1_glue);
|
|
dwc3_uboot_init(&usb_otg_ss1);
|
|
break;
|
|
case 1:
|
|
if (init == USB_INIT_DEVICE) {
|
|
usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
|
|
usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
|
|
} else {
|
|
usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
|
|
usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
|
|
}
|
|
|
|
ti_usb_phy_uboot_init(&usb_phy2_device);
|
|
dwc3_omap_uboot_init(&usb_otg_ss2_glue);
|
|
dwc3_uboot_init(&usb_otg_ss2);
|
|
break;
|
|
default:
|
|
printf("Invalid Controller Index\n");
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int board_usb_cleanup(int index, enum usb_init_type init)
|
|
{
|
|
switch (index) {
|
|
case 0:
|
|
case 1:
|
|
ti_usb_phy_uboot_exit(index);
|
|
dwc3_uboot_exit(index);
|
|
dwc3_omap_uboot_exit(index);
|
|
break;
|
|
default:
|
|
printf("Invalid Controller Index\n");
|
|
}
|
|
disable_usb_clocks(index);
|
|
return 0;
|
|
}
|
|
|
|
int usb_gadget_handle_interrupts(int index)
|
|
{
|
|
u32 status;
|
|
|
|
status = dwc3_omap_uboot_interrupt_status(index);
|
|
if (status)
|
|
dwc3_uboot_handle_interrupt(index);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
|
|
int spl_start_uboot(void)
|
|
{
|
|
/* break into full u-boot on 'c' */
|
|
if (serial_tstc() && serial_getc() == 'c')
|
|
return 1;
|
|
|
|
#ifdef CONFIG_SPL_ENV_SUPPORT
|
|
env_init();
|
|
env_load();
|
|
if (env_get_yesno("boot_os") != 1)
|
|
return 1;
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_DRIVER_TI_CPSW
|
|
extern u32 *const omap_si_rev;
|
|
|
|
static void cpsw_control(int enabled)
|
|
{
|
|
/* VTP can be added here */
|
|
|
|
return;
|
|
}
|
|
|
|
static struct cpsw_slave_data cpsw_slaves[] = {
|
|
{
|
|
.slave_reg_ofs = 0x208,
|
|
.sliver_reg_ofs = 0xd80,
|
|
.phy_addr = 2,
|
|
},
|
|
{
|
|
.slave_reg_ofs = 0x308,
|
|
.sliver_reg_ofs = 0xdc0,
|
|
.phy_addr = 3,
|
|
},
|
|
};
|
|
|
|
static struct cpsw_platform_data cpsw_data = {
|
|
.mdio_base = CPSW_MDIO_BASE,
|
|
.cpsw_base = CPSW_BASE,
|
|
.mdio_div = 0xff,
|
|
.channels = 8,
|
|
.cpdma_reg_ofs = 0x800,
|
|
.slaves = 2,
|
|
.slave_data = cpsw_slaves,
|
|
.ale_reg_ofs = 0xd00,
|
|
.ale_entries = 1024,
|
|
.host_port_reg_ofs = 0x108,
|
|
.hw_stats_reg_ofs = 0x900,
|
|
.bd_ram_ofs = 0x2000,
|
|
.mac_control = (1 << 5),
|
|
.control = cpsw_control,
|
|
.host_port_num = 0,
|
|
.version = CPSW_CTRL_VERSION_2,
|
|
};
|
|
|
|
int board_eth_init(bd_t *bis)
|
|
{
|
|
int ret;
|
|
uint8_t mac_addr[6];
|
|
uint32_t mac_hi, mac_lo;
|
|
uint32_t ctrl_val;
|
|
|
|
/* try reading mac address from efuse */
|
|
mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
|
|
mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
|
|
mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
|
|
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
|
|
mac_addr[2] = mac_hi & 0xFF;
|
|
mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
|
|
mac_addr[4] = (mac_lo & 0xFF00) >> 8;
|
|
mac_addr[5] = mac_lo & 0xFF;
|
|
|
|
if (!env_get("ethaddr")) {
|
|
printf("<ethaddr> not set. Validating first E-fuse MAC\n");
|
|
|
|
if (is_valid_ethaddr(mac_addr))
|
|
eth_env_set_enetaddr("ethaddr", mac_addr);
|
|
}
|
|
|
|
mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
|
|
mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
|
|
mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
|
|
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
|
|
mac_addr[2] = mac_hi & 0xFF;
|
|
mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
|
|
mac_addr[4] = (mac_lo & 0xFF00) >> 8;
|
|
mac_addr[5] = mac_lo & 0xFF;
|
|
|
|
if (!env_get("eth1addr")) {
|
|
if (is_valid_ethaddr(mac_addr))
|
|
eth_env_set_enetaddr("eth1addr", mac_addr);
|
|
}
|
|
|
|
ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
|
|
ctrl_val |= 0x22;
|
|
writel(ctrl_val, (*ctrl)->control_core_control_io1);
|
|
|
|
if (*omap_si_rev == DRA722_ES1_0)
|
|
cpsw_data.active_slave = 1;
|
|
|
|
if (board_is_dra72x_revc_or_later()) {
|
|
cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
|
|
cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
|
|
}
|
|
|
|
ret = cpsw_register(&cpsw_data);
|
|
if (ret < 0)
|
|
printf("Error %d registering CPSW switch\n", ret);
|
|
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_BOARD_EARLY_INIT_F
|
|
/* VTT regulator enable */
|
|
static inline void vtt_regulator_enable(void)
|
|
{
|
|
if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
|
|
return;
|
|
|
|
/* Do not enable VTT for DRA722 or DRA76x */
|
|
if (is_dra72x() || is_dra76x())
|
|
return;
|
|
|
|
/*
|
|
* EVM Rev G and later use gpio7_11 for DDR3 termination.
|
|
* This is safe enough to do on older revs.
|
|
*/
|
|
gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
|
|
gpio_direction_output(GPIO_DDR_VTT_EN, 1);
|
|
}
|
|
|
|
int board_early_init_f(void)
|
|
{
|
|
vtt_regulator_enable();
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
|
|
int ft_board_setup(void *blob, bd_t *bd)
|
|
{
|
|
ft_cpu_setup(blob, bd);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_SPL_LOAD_FIT
|
|
int board_fit_config_name_match(const char *name)
|
|
{
|
|
if (is_dra72x()) {
|
|
if (board_is_dra71x_evm()) {
|
|
if (!strcmp(name, "dra71-evm"))
|
|
return 0;
|
|
}else if(board_is_dra72x_revc_or_later()) {
|
|
if (!strcmp(name, "dra72-evm-revc"))
|
|
return 0;
|
|
} else if (!strcmp(name, "dra72-evm")) {
|
|
return 0;
|
|
}
|
|
} else if (is_dra76x_acd() && !strcmp(name, "dra76-evm")) {
|
|
return 0;
|
|
} else if (!is_dra72x() && !is_dra76x_acd() &&
|
|
!strcmp(name, "dra7-evm")) {
|
|
return 0;
|
|
}
|
|
|
|
return -1;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_TI_SECURE_DEVICE
|
|
void board_fit_image_post_process(void **p_image, size_t *p_size)
|
|
{
|
|
secure_boot_verify_image(p_image, p_size);
|
|
}
|
|
|
|
void board_tee_image_process(ulong tee_image, size_t tee_size)
|
|
{
|
|
secure_tee_install((u32)tee_image);
|
|
}
|
|
|
|
U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
|
|
#endif
|
|
|