upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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528 lines
17 KiB
528 lines
17 KiB
/*
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* Copyright (C) 2004 PaulReynolds@lhsolutions.com
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*
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* (C) Copyright 2005
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include "ocotea.h"
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#include <asm/processor.h>
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#include <spd_sdram.h>
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#include <ppc4xx_enet.h>
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#define BOOT_SMALL_FLASH 32 /* 00100000 */
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#define FLASH_ONBD_N 2 /* 00000010 */
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#define FLASH_SRAM_SEL 1 /* 00000001 */
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long int fixed_sdram (void);
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void fpga_init (void);
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int board_early_init_f (void)
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{
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unsigned long mfr;
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unsigned char *fpga_base = (unsigned char *) CFG_FPGA_BASE;
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unsigned char switch_status;
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unsigned long cs0_base;
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unsigned long cs0_size;
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unsigned long cs0_twt;
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unsigned long cs2_base;
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unsigned long cs2_size;
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unsigned long cs2_twt;
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/*-------------------------------------------------------------------------+
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| Initialize EBC CONFIG
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+-------------------------------------------------------------------------*/
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mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
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EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
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EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
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EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
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EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
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/*-------------------------------------------------------------------------+
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| FPGA. Initialize bank 7 with default values.
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+-------------------------------------------------------------------------*/
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mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
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EBC_BXAP_BCE_DISABLE|
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EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
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EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
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EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
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EBC_BXAP_BEM_WRITEONLY|
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EBC_BXAP_PEN_DISABLED);
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mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)|
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EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
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/* read FPGA base register FPGA_REG0 */
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switch_status = *fpga_base;
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if (switch_status & 0x40) {
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cs0_base = 0xFFE00000;
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cs0_size = EBC_BXCR_BS_2MB;
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cs0_twt = 8;
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cs2_base = 0xFF800000;
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cs2_size = EBC_BXCR_BS_4MB;
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cs2_twt = 10;
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} else {
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cs0_base = 0xFFC00000;
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cs0_size = EBC_BXCR_BS_4MB;
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cs0_twt = 10;
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cs2_base = 0xFF800000;
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cs2_size = EBC_BXCR_BS_2MB;
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cs2_twt = 8;
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}
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/*-------------------------------------------------------------------------+
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| 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values.
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+-------------------------------------------------------------------------*/
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mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs0_twt)|
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EBC_BXAP_BCE_DISABLE|
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EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
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EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
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EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
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EBC_BXAP_BEM_WRITEONLY|
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EBC_BXAP_PEN_DISABLED);
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mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(cs0_base)|
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cs0_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
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/*-------------------------------------------------------------------------+
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| 8KB NVRAM/RTC. Initialize bank 1 with default values.
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+-------------------------------------------------------------------------*/
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mtebc(pb1ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)|
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EBC_BXAP_BCE_DISABLE|
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EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
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EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
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EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
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EBC_BXAP_BEM_WRITEONLY|
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EBC_BXAP_PEN_DISABLED);
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mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000)|
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EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
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/*-------------------------------------------------------------------------+
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| 4 MB FLASH. Initialize bank 2 with default values.
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+-------------------------------------------------------------------------*/
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mtebc(pb2ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs2_twt)|
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EBC_BXAP_BCE_DISABLE|
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EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
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EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
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EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
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EBC_BXAP_BEM_WRITEONLY|
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EBC_BXAP_PEN_DISABLED);
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mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(cs2_base)|
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cs2_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
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/*-------------------------------------------------------------------------+
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| FPGA. Initialize bank 7 with default values.
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+-------------------------------------------------------------------------*/
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mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
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EBC_BXAP_BCE_DISABLE|
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EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
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EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
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EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
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EBC_BXAP_BEM_WRITEONLY|
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EBC_BXAP_PEN_DISABLED);
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mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)|
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EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
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/*--------------------------------------------------------------------
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* Setup the interrupt controller polarities, triggers, etc.
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*-------------------------------------------------------------------*/
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mtdcr (uic0sr, 0xffffffff); /* clear all */
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mtdcr (uic0er, 0x00000000); /* disable all */
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mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
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mtdcr (uic0pr, 0xfffffe13); /* per ref-board manual */
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mtdcr (uic0tr, 0x01c00008); /* per ref-board manual */
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mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr (uic0sr, 0xffffffff); /* clear all */
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mtdcr (uic1sr, 0xffffffff); /* clear all */
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mtdcr (uic1er, 0x00000000); /* disable all */
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mtdcr (uic1cr, 0x00000000); /* all non-critical */
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mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */
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mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */
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mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr (uic1sr, 0xffffffff); /* clear all */
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mtdcr (uic2sr, 0xffffffff); /* clear all */
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mtdcr (uic2er, 0x00000000); /* disable all */
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mtdcr (uic2cr, 0x00000000); /* all non-critical */
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mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */
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mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */
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mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr (uic2sr, 0xffffffff); /* clear all */
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mtdcr (uicb0sr, 0xfc000000); /* clear all */
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mtdcr (uicb0er, 0x00000000); /* disable all */
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mtdcr (uicb0cr, 0x00000000); /* all non-critical */
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mtdcr (uicb0pr, 0xfc000000); /* */
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mtdcr (uicb0tr, 0x00000000); /* */
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mtdcr (uicb0vr, 0x00000001); /* */
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mfsdr (sdr_mfr, mfr);
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mfr &= ~SDR0_MFR_ECS_MASK;
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/* mtsdr(sdr_mfr, mfr); */
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fpga_init();
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return 0;
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}
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int checkboard (void)
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{
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char *s = getenv ("serial#");
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printf ("Board: Ocotea - AMCC PPC440GX Evaluation Board");
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if (s != NULL) {
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puts (", serial# ");
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puts (s);
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}
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putc ('\n');
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return (0);
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}
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long int initdram (int board_type)
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{
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long dram_size = 0;
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#if defined(CONFIG_SPD_EEPROM)
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dram_size = spd_sdram (0);
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#else
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dram_size = fixed_sdram ();
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#endif
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return dram_size;
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}
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#if defined(CFG_DRAM_TEST)
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int testdram (void)
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{
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uint *pstart = (uint *) 0x00000000;
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uint *pend = (uint *) 0x08000000;
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uint *p;
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for (p = pstart; p < pend; p++)
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*p = 0xaaaaaaaa;
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for (p = pstart; p < pend; p++) {
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if (*p != 0xaaaaaaaa) {
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printf ("SDRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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for (p = pstart; p < pend; p++)
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*p = 0x55555555;
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for (p = pstart; p < pend; p++) {
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if (*p != 0x55555555) {
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printf ("SDRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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return 0;
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}
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#endif
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#if !defined(CONFIG_SPD_EEPROM)
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/*************************************************************************
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* fixed sdram init -- doesn't use serial presence detect.
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*
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* Assumes: 128 MB, non-ECC, non-registered
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* PLB @ 133 MHz
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*
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************************************************************************/
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long int fixed_sdram (void)
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{
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uint reg;
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/*--------------------------------------------------------------------
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* Setup some default
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*------------------------------------------------------------------*/
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mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */
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mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
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mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
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mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
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mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
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/*--------------------------------------------------------------------
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* Setup for board-specific specific mem
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*------------------------------------------------------------------*/
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/*
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* Following for CAS Latency = 2.5 @ 133 MHz PLB
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*/
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mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
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mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
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/* RA=10 RD=3 */
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mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
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mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
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mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
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udelay (400); /* Delay 200 usecs (min) */
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/*--------------------------------------------------------------------
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* Enable the controller, then wait for DCEN to complete
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*------------------------------------------------------------------*/
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mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
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for (;;) {
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mfsdram (mem_mcsts, reg);
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if (reg & 0x80000000)
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break;
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}
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return (128 * 1024 * 1024); /* 128 MB */
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}
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#endif /* !defined(CONFIG_SPD_EEPROM) */
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/*************************************************************************
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* pci_pre_init
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*
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* This routine is called just prior to registering the hose and gives
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* the board the opportunity to check things. Returning a value of zero
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* indicates that things are bad & PCI initialization should be aborted.
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*
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* Different boards may wish to customize the pci controller structure
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* (add regions, override default access routines, etc) or perform
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* certain pre-initialization actions.
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*
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************************************************************************/
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#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
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int pci_pre_init(struct pci_controller * hose )
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{
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unsigned long strap;
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/*--------------------------------------------------------------------------+
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* The ocotea board is always configured as the host & requires the
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* PCI arbiter to be enabled.
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*--------------------------------------------------------------------------*/
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mfsdr(sdr_sdstp1, strap);
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if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
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printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
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return 0;
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}
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return 1;
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}
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#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
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/*************************************************************************
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* pci_target_init
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*
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* The bootstrap configuration provides default settings for the pci
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* inbound map (PIM). But the bootstrap config choices are limited and
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* may not be sufficient for a given board.
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*
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************************************************************************/
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#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
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void pci_target_init(struct pci_controller * hose )
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{
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DECLARE_GLOBAL_DATA_PTR;
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/*--------------------------------------------------------------------------+
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* Disable everything
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*--------------------------------------------------------------------------*/
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out32r( PCIX0_PIM0SA, 0 ); /* disable */
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out32r( PCIX0_PIM1SA, 0 ); /* disable */
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out32r( PCIX0_PIM2SA, 0 ); /* disable */
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out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
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/*--------------------------------------------------------------------------+
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* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
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* options to not support sizes such as 128/256 MB.
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*--------------------------------------------------------------------------*/
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out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
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out32r( PCIX0_PIM0LAH, 0 );
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out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
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out32r( PCIX0_BAR0, 0 );
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/*--------------------------------------------------------------------------+
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* Program the board's subsystem id/vendor id
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*--------------------------------------------------------------------------*/
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out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
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out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
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out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
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}
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#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
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/*************************************************************************
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* is_pci_host
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*
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* This routine is called to determine if a pci scan should be
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* performed. With various hardware environments (especially cPCI and
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* PPMC) it's insufficient to depend on the state of the arbiter enable
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* bit in the strap register, or generic host/adapter assumptions.
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*
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* Rather than hard-code a bad assumption in the general 440 code, the
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* 440 pci code requires the board to decide at runtime.
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*
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* Return 0 for adapter mode, non-zero for host (monarch) mode.
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*
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*
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************************************************************************/
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#if defined(CONFIG_PCI)
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int is_pci_host(struct pci_controller *hose)
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{
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/* The ocotea board is always configured as host. */
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return(1);
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}
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#endif /* defined(CONFIG_PCI) */
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void fpga_init(void)
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{
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unsigned long group;
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unsigned long sdr0_pfc0;
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unsigned long sdr0_pfc1;
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unsigned long sdr0_cust0;
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unsigned long pvr;
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mfsdr (sdr_pfc0, sdr0_pfc0);
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mfsdr (sdr_pfc1, sdr0_pfc1);
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group = SDR0_PFC1_EPS_DECODE(sdr0_pfc1);
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pvr = get_pvr ();
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sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_GEIE_MASK) | SDR0_PFC0_GEIE_TRE;
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if ( ((pvr == PVR_440GX_RA) || (pvr == PVR_440GX_RB)) && ((group == 4) || (group == 5))) {
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sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_DISABLE;
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sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
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out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
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FPGA_REG2_EXT_INTFACE_ENABLE);
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mtsdr (sdr_pfc0, sdr0_pfc0);
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mtsdr (sdr_pfc1, sdr0_pfc1);
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} else {
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sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_ENABLE;
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switch (group)
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{
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case 0:
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case 1:
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case 2:
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/* CPU trace A */
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out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
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FPGA_REG2_EXT_INTFACE_ENABLE);
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sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
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mtsdr (sdr_pfc0, sdr0_pfc0);
|
|
mtsdr (sdr_pfc1, sdr0_pfc1);
|
|
break;
|
|
case 3:
|
|
case 4:
|
|
case 5:
|
|
case 6:
|
|
/* CPU trace B - Over EBMI */
|
|
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_CPUTRACE;
|
|
mtsdr (sdr_pfc0, sdr0_pfc0);
|
|
mtsdr (sdr_pfc1, sdr0_pfc1);
|
|
out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
|
|
FPGA_REG2_EXT_INTFACE_DISABLE);
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* Initialize the ethernet specific functions in the fpga */
|
|
mfsdr(sdr_pfc1, sdr0_pfc1);
|
|
mfsdr(sdr_cust0, sdr0_cust0);
|
|
if ( (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) == 4) &&
|
|
((SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) ||
|
|
(SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_TBI)))
|
|
{
|
|
if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
|
|
{
|
|
out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) |
|
|
FPGA_REG3_ENET_GROUP7);
|
|
}
|
|
else
|
|
{
|
|
if (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII)
|
|
{
|
|
out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
|
|
FPGA_REG3_ENET_GROUP7);
|
|
}
|
|
else
|
|
{
|
|
out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
|
|
FPGA_REG3_ENET_GROUP8);
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
|
|
{
|
|
out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) |
|
|
FPGA_REG3_ENET_ENCODE1(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
|
|
}
|
|
else
|
|
{
|
|
out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
|
|
FPGA_REG3_ENET_ENCODE2(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
|
|
}
|
|
}
|
|
out8(FPGA_REG4, FPGA_REG4_GPHY_MODE10 |
|
|
FPGA_REG4_GPHY_MODE100 | FPGA_REG4_GPHY_MODE1000 |
|
|
FPGA_REG4_GPHY_FRC_DPLX | FPGA_REG4_CONNECT_PHYS);
|
|
|
|
/* reset the gigabyte phy if necessary */
|
|
if (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) >= 3)
|
|
{
|
|
if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
|
|
{
|
|
out8(FPGA_REG3, in8(FPGA_REG3) & ~FPGA_REG3_GIGABIT_RESET_DISABLE);
|
|
udelay(10000);
|
|
out8(FPGA_REG3, in8(FPGA_REG3) | FPGA_REG3_GIGABIT_RESET_DISABLE);
|
|
}
|
|
else
|
|
{
|
|
out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_GIGABIT_RESET_DISABLE);
|
|
udelay(10000);
|
|
out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_GIGABIT_RESET_DISABLE);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* new Ocotea with Rev. F (pass 3) chips has SMII PHY reset
|
|
*/
|
|
if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER2) {
|
|
out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_SMII_RESET_DISABLE);
|
|
udelay(10000);
|
|
out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_SMII_RESET_DISABLE);
|
|
}
|
|
|
|
/* Turn off the LED's */
|
|
out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_STAT_MASK) |
|
|
FPGA_REG3_STAT_LED8_DISAB | FPGA_REG3_STAT_LED4_DISAB |
|
|
FPGA_REG3_STAT_LED2_DISAB | FPGA_REG3_STAT_LED1_DISAB);
|
|
|
|
return;
|
|
}
|
|
|
|
#ifdef CONFIG_POST
|
|
/*
|
|
* Returns 1 if keys pressed to start the power-on long-running tests
|
|
* Called from board_init_f().
|
|
*/
|
|
int post_hotkeys_pressed(void)
|
|
{
|
|
|
|
return (ctrlc());
|
|
}
|
|
#endif
|
|
|