upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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631 lines
15 KiB
631 lines
15 KiB
/*
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* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
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* Copyright (c) 2010-2011 NVIDIA Corporation
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* NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <fdtdec.h>
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#include <i2c.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/funcmux.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch-tegra/clk_rst.h>
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#include <asm/arch-tegra/tegra_i2c.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* Information about i2c controller */
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struct i2c_bus {
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int id;
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enum periph_id periph_id;
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int speed;
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int pinmux_config;
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struct i2c_control *control;
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struct i2c_ctlr *regs;
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int is_dvc; /* DVC type, rather than I2C */
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int is_scs; /* single clock source (T114+) */
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int inited; /* bus is inited */
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};
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static struct i2c_bus i2c_controllers[TEGRA_I2C_NUM_CONTROLLERS];
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static void set_packet_mode(struct i2c_bus *i2c_bus)
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{
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u32 config;
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config = I2C_CNFG_NEW_MASTER_FSM_MASK | I2C_CNFG_PACKET_MODE_MASK;
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if (i2c_bus->is_dvc) {
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struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs;
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writel(config, &dvc->cnfg);
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} else {
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writel(config, &i2c_bus->regs->cnfg);
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/*
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* program I2C_SL_CNFG.NEWSL to ENABLE. This fixes probe
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* issues, i.e., some slaves may be wrongly detected.
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*/
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setbits_le32(&i2c_bus->regs->sl_cnfg, I2C_SL_CNFG_NEWSL_MASK);
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}
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}
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static void i2c_reset_controller(struct i2c_bus *i2c_bus)
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{
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/* Reset I2C controller. */
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reset_periph(i2c_bus->periph_id, 1);
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/* re-program config register to packet mode */
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set_packet_mode(i2c_bus);
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}
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static void i2c_init_controller(struct i2c_bus *i2c_bus)
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{
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/*
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* Use PLLP - DP-04508-001_v06 datasheet indicates a divisor of 8
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* here, in section 23.3.1, but in fact we seem to need a factor of
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* 16 to get the right frequency.
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*/
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clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH,
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i2c_bus->speed * 2 * 8);
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if (i2c_bus->is_scs) {
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/*
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* T114 I2C went to a single clock source for standard/fast and
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* HS clock speeds. The new clock rate setting calculation is:
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* SCL = CLK_SOURCE.I2C /
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* (CLK_MULT_STD_FAST_MODE * (I2C_CLK_DIV_STD_FAST_MODE+1) *
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* I2C FREQUENCY DIVISOR) as per the T114 TRM (sec 30.3.1).
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*
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* NOTE: We do this here, after the initial clock/pll start,
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* because if we read the clk_div reg before the controller
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* is running, we hang, and we need it for the new calc.
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*/
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int clk_div_stdfst_mode = readl(&i2c_bus->regs->clk_div) >> 16;
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debug("%s: CLK_DIV_STD_FAST_MODE setting = %d\n", __func__,
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clk_div_stdfst_mode);
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clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH,
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CLK_MULT_STD_FAST_MODE * (clk_div_stdfst_mode + 1) *
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i2c_bus->speed * 2);
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}
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/* Reset I2C controller. */
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i2c_reset_controller(i2c_bus);
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/* Configure I2C controller. */
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if (i2c_bus->is_dvc) { /* only for DVC I2C */
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struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs;
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setbits_le32(&dvc->ctrl3, DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK);
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}
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funcmux_select(i2c_bus->periph_id, i2c_bus->pinmux_config);
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}
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static void send_packet_headers(
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struct i2c_bus *i2c_bus,
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struct i2c_trans_info *trans,
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u32 packet_id)
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{
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u32 data;
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/* prepare header1: Header size = 0 Protocol = I2C, pktType = 0 */
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data = PROTOCOL_TYPE_I2C << PKT_HDR1_PROTOCOL_SHIFT;
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data |= packet_id << PKT_HDR1_PKT_ID_SHIFT;
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data |= i2c_bus->id << PKT_HDR1_CTLR_ID_SHIFT;
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writel(data, &i2c_bus->control->tx_fifo);
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debug("pkt header 1 sent (0x%x)\n", data);
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/* prepare header2 */
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data = (trans->num_bytes - 1) << PKT_HDR2_PAYLOAD_SIZE_SHIFT;
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writel(data, &i2c_bus->control->tx_fifo);
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debug("pkt header 2 sent (0x%x)\n", data);
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/* prepare IO specific header: configure the slave address */
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data = trans->address << PKT_HDR3_SLAVE_ADDR_SHIFT;
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/* Enable Read if it is not a write transaction */
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if (!(trans->flags & I2C_IS_WRITE))
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data |= PKT_HDR3_READ_MODE_MASK;
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/* Write I2C specific header */
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writel(data, &i2c_bus->control->tx_fifo);
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debug("pkt header 3 sent (0x%x)\n", data);
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}
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static int wait_for_tx_fifo_empty(struct i2c_control *control)
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{
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u32 count;
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int timeout_us = I2C_TIMEOUT_USEC;
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while (timeout_us >= 0) {
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count = (readl(&control->fifo_status) & TX_FIFO_EMPTY_CNT_MASK)
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>> TX_FIFO_EMPTY_CNT_SHIFT;
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if (count == I2C_FIFO_DEPTH)
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return 1;
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udelay(10);
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timeout_us -= 10;
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}
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return 0;
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}
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static int wait_for_rx_fifo_notempty(struct i2c_control *control)
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{
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u32 count;
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int timeout_us = I2C_TIMEOUT_USEC;
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while (timeout_us >= 0) {
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count = (readl(&control->fifo_status) & TX_FIFO_FULL_CNT_MASK)
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>> TX_FIFO_FULL_CNT_SHIFT;
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if (count)
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return 1;
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udelay(10);
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timeout_us -= 10;
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}
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return 0;
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}
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static int wait_for_transfer_complete(struct i2c_control *control)
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{
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int int_status;
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int timeout_us = I2C_TIMEOUT_USEC;
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while (timeout_us >= 0) {
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int_status = readl(&control->int_status);
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if (int_status & I2C_INT_NO_ACK_MASK)
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return -int_status;
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if (int_status & I2C_INT_ARBITRATION_LOST_MASK)
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return -int_status;
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if (int_status & I2C_INT_XFER_COMPLETE_MASK)
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return 0;
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udelay(10);
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timeout_us -= 10;
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}
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return -1;
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}
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static int send_recv_packets(struct i2c_bus *i2c_bus,
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struct i2c_trans_info *trans)
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{
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struct i2c_control *control = i2c_bus->control;
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u32 int_status;
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u32 words;
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u8 *dptr;
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u32 local;
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uchar last_bytes;
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int error = 0;
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int is_write = trans->flags & I2C_IS_WRITE;
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/* clear status from previous transaction, XFER_COMPLETE, NOACK, etc. */
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int_status = readl(&control->int_status);
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writel(int_status, &control->int_status);
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send_packet_headers(i2c_bus, trans, 1);
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words = DIV_ROUND_UP(trans->num_bytes, 4);
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last_bytes = trans->num_bytes & 3;
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dptr = trans->buf;
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while (words) {
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u32 *wptr = (u32 *)dptr;
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if (is_write) {
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/* deal with word alignment */
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if ((unsigned)dptr & 3) {
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memcpy(&local, dptr, sizeof(u32));
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writel(local, &control->tx_fifo);
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debug("pkt data sent (0x%x)\n", local);
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} else {
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writel(*wptr, &control->tx_fifo);
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debug("pkt data sent (0x%x)\n", *wptr);
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}
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if (!wait_for_tx_fifo_empty(control)) {
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error = -1;
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goto exit;
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}
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} else {
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if (!wait_for_rx_fifo_notempty(control)) {
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error = -1;
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goto exit;
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}
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/*
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* for the last word, we read into our local buffer,
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* in case that caller did not provide enough buffer.
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*/
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local = readl(&control->rx_fifo);
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if ((words == 1) && last_bytes)
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memcpy(dptr, (char *)&local, last_bytes);
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else if ((unsigned)dptr & 3)
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memcpy(dptr, &local, sizeof(u32));
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else
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*wptr = local;
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debug("pkt data received (0x%x)\n", local);
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}
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words--;
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dptr += sizeof(u32);
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}
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if (wait_for_transfer_complete(control)) {
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error = -1;
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goto exit;
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}
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return 0;
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exit:
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/* error, reset the controller. */
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i2c_reset_controller(i2c_bus);
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return error;
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}
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static int tegra_i2c_write_data(struct i2c_bus *bus, u32 addr, u8 *data,
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u32 len)
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{
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int error;
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struct i2c_trans_info trans_info;
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trans_info.address = addr;
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trans_info.buf = data;
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trans_info.flags = I2C_IS_WRITE;
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trans_info.num_bytes = len;
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trans_info.is_10bit_address = 0;
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error = send_recv_packets(bus, &trans_info);
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if (error)
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debug("tegra_i2c_write_data: Error (%d) !!!\n", error);
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return error;
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}
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static int tegra_i2c_read_data(struct i2c_bus *bus, u32 addr, u8 *data,
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u32 len)
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{
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int error;
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struct i2c_trans_info trans_info;
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trans_info.address = addr | 1;
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trans_info.buf = data;
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trans_info.flags = 0;
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trans_info.num_bytes = len;
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trans_info.is_10bit_address = 0;
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error = send_recv_packets(bus, &trans_info);
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if (error)
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debug("tegra_i2c_read_data: Error (%d) !!!\n", error);
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return error;
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}
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#ifndef CONFIG_OF_CONTROL
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#error "Please enable device tree support to use this driver"
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#endif
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/**
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* Check that a bus number is valid and return a pointer to it
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*
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* @param bus_num Bus number to check / return
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* @return pointer to bus, if valid, else NULL
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*/
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static struct i2c_bus *tegra_i2c_get_bus(struct i2c_adapter *adap)
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{
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struct i2c_bus *bus;
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bus = &i2c_controllers[adap->hwadapnr];
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if (!bus->inited) {
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debug("%s: Bus %u not available\n", __func__, adap->hwadapnr);
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return NULL;
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}
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return bus;
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}
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static unsigned int tegra_i2c_set_bus_speed(struct i2c_adapter *adap,
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unsigned int speed)
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{
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struct i2c_bus *bus;
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bus = tegra_i2c_get_bus(adap);
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if (!bus)
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return 0;
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bus->speed = speed;
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i2c_init_controller(bus);
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return 0;
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}
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static int i2c_get_config(const void *blob, int node, struct i2c_bus *i2c_bus)
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{
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i2c_bus->regs = (struct i2c_ctlr *)fdtdec_get_addr(blob, node, "reg");
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/*
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* We don't have a binding for pinmux yet. Leave it out for now. So
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* far no one needs anything other than the default.
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*/
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i2c_bus->pinmux_config = FUNCMUX_DEFAULT;
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i2c_bus->speed = fdtdec_get_int(blob, node, "clock-frequency", 0);
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i2c_bus->periph_id = clock_decode_periph_id(blob, node);
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/*
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* We can't specify the pinmux config in the fdt, so I2C2 will not
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* work on Seaboard. It normally has no devices on it anyway.
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* You could add in this little hack if you need to use it.
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* The correct solution is a pinmux binding in the fdt.
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*
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* if (i2c_bus->periph_id == PERIPH_ID_I2C2)
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* i2c_bus->pinmux_config = FUNCMUX_I2C2_PTA;
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*/
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if (i2c_bus->periph_id == -1)
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return -FDT_ERR_NOTFOUND;
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return 0;
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}
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/*
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* Process a list of nodes, adding them to our list of I2C ports.
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*
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* @param blob fdt blob
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* @param node_list list of nodes to process (any <=0 are ignored)
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* @param count number of nodes to process
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* @param is_dvc 1 if these are DVC ports, 0 if standard I2C
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* @param is_scs 1 if this HW uses a single clock source (T114+)
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* @return 0 if ok, -1 on error
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*/
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static int process_nodes(const void *blob, int node_list[], int count,
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int is_dvc, int is_scs)
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{
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struct i2c_bus *i2c_bus;
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int i;
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/* build the i2c_controllers[] for each controller */
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for (i = 0; i < count; i++) {
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int node = node_list[i];
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if (node <= 0)
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continue;
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i2c_bus = &i2c_controllers[i];
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i2c_bus->id = i;
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if (i2c_get_config(blob, node, i2c_bus)) {
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printf("i2c_init_board: failed to decode bus %d\n", i);
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return -1;
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}
|
|
|
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i2c_bus->is_scs = is_scs;
|
|
|
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i2c_bus->is_dvc = is_dvc;
|
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if (is_dvc) {
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i2c_bus->control =
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&((struct dvc_ctlr *)i2c_bus->regs)->control;
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} else {
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i2c_bus->control = &i2c_bus->regs->control;
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}
|
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debug("%s: controller bus %d at %p, periph_id %d, speed %d: ",
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is_dvc ? "dvc" : "i2c", i, i2c_bus->regs,
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i2c_bus->periph_id, i2c_bus->speed);
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i2c_init_controller(i2c_bus);
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debug("ok\n");
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i2c_bus->inited = 1;
|
|
|
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/* Mark position as used */
|
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node_list[i] = -1;
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}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Sadly there is no error return from this function */
|
|
void i2c_init_board(void)
|
|
{
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int node_list[TEGRA_I2C_NUM_CONTROLLERS];
|
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const void *blob = gd->fdt_blob;
|
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int count;
|
|
|
|
/* First check for newer (T114+) I2C ports */
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count = fdtdec_find_aliases_for_id(blob, "i2c",
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COMPAT_NVIDIA_TEGRA114_I2C, node_list,
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TEGRA_I2C_NUM_CONTROLLERS);
|
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if (process_nodes(blob, node_list, count, 0, 1))
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return;
|
|
|
|
/* Now get the older (T20/T30) normal I2C ports */
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|
count = fdtdec_find_aliases_for_id(blob, "i2c",
|
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COMPAT_NVIDIA_TEGRA20_I2C, node_list,
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TEGRA_I2C_NUM_CONTROLLERS);
|
|
if (process_nodes(blob, node_list, count, 0, 0))
|
|
return;
|
|
|
|
/* Now look for dvc ports */
|
|
count = fdtdec_add_aliases_for_id(blob, "i2c",
|
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COMPAT_NVIDIA_TEGRA20_DVC, node_list,
|
|
TEGRA_I2C_NUM_CONTROLLERS);
|
|
if (process_nodes(blob, node_list, count, 1, 0))
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return;
|
|
}
|
|
|
|
static void tegra_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
|
|
{
|
|
/* No i2c support prior to relocation */
|
|
if (!(gd->flags & GD_FLG_RELOC))
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return;
|
|
|
|
/* This will override the speed selected in the fdt for that port */
|
|
debug("i2c_init(speed=%u, slaveaddr=0x%x)\n", speed, slaveaddr);
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i2c_set_bus_speed(speed);
|
|
}
|
|
|
|
/* i2c write version without the register address */
|
|
int i2c_write_data(struct i2c_bus *bus, uchar chip, uchar *buffer, int len)
|
|
{
|
|
int rc;
|
|
|
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debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
|
|
debug("write_data: ");
|
|
/* use rc for counter */
|
|
for (rc = 0; rc < len; ++rc)
|
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debug(" 0x%02x", buffer[rc]);
|
|
debug("\n");
|
|
|
|
/* Shift 7-bit address over for lower-level i2c functions */
|
|
rc = tegra_i2c_write_data(bus, chip << 1, buffer, len);
|
|
if (rc)
|
|
debug("i2c_write_data(): rc=%d\n", rc);
|
|
|
|
return rc;
|
|
}
|
|
|
|
/* i2c read version without the register address */
|
|
int i2c_read_data(struct i2c_bus *bus, uchar chip, uchar *buffer, int len)
|
|
{
|
|
int rc;
|
|
|
|
debug("inside i2c_read_data():\n");
|
|
/* Shift 7-bit address over for lower-level i2c functions */
|
|
rc = tegra_i2c_read_data(bus, chip << 1, buffer, len);
|
|
if (rc) {
|
|
debug("i2c_read_data(): rc=%d\n", rc);
|
|
return rc;
|
|
}
|
|
|
|
debug("i2c_read_data: ");
|
|
/* reuse rc for counter*/
|
|
for (rc = 0; rc < len; ++rc)
|
|
debug(" 0x%02x", buffer[rc]);
|
|
debug("\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Probe to see if a chip is present. */
|
|
static int tegra_i2c_probe(struct i2c_adapter *adap, uchar chip)
|
|
{
|
|
struct i2c_bus *bus;
|
|
int rc;
|
|
uchar reg;
|
|
|
|
debug("i2c_probe: addr=0x%x\n", chip);
|
|
bus = tegra_i2c_get_bus(adap);
|
|
if (!bus)
|
|
return 1;
|
|
reg = 0;
|
|
rc = i2c_write_data(bus, chip, ®, 1);
|
|
if (rc) {
|
|
debug("Error probing 0x%x.\n", chip);
|
|
return 1;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int i2c_addr_ok(const uint addr, const int alen)
|
|
{
|
|
/* We support 7 or 10 bit addresses, so one or two bytes each */
|
|
return alen == 1 || alen == 2;
|
|
}
|
|
|
|
/* Read bytes */
|
|
static int tegra_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
|
|
int alen, uchar *buffer, int len)
|
|
{
|
|
struct i2c_bus *bus;
|
|
uint offset;
|
|
int i;
|
|
|
|
debug("i2c_read: chip=0x%x, addr=0x%x, len=0x%x\n",
|
|
chip, addr, len);
|
|
bus = tegra_i2c_get_bus(adap);
|
|
if (!bus)
|
|
return 1;
|
|
if (!i2c_addr_ok(addr, alen)) {
|
|
debug("i2c_read: Bad address %x.%d.\n", addr, alen);
|
|
return 1;
|
|
}
|
|
for (offset = 0; offset < len; offset++) {
|
|
if (alen) {
|
|
uchar data[alen];
|
|
for (i = 0; i < alen; i++) {
|
|
data[alen - i - 1] =
|
|
(addr + offset) >> (8 * i);
|
|
}
|
|
if (i2c_write_data(bus, chip, data, alen)) {
|
|
debug("i2c_read: error sending (0x%x)\n",
|
|
addr);
|
|
return 1;
|
|
}
|
|
}
|
|
if (i2c_read_data(bus, chip, buffer + offset, 1)) {
|
|
debug("i2c_read: error reading (0x%x)\n", addr);
|
|
return 1;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Write bytes */
|
|
static int tegra_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
|
|
int alen, uchar *buffer, int len)
|
|
{
|
|
struct i2c_bus *bus;
|
|
uint offset;
|
|
int i;
|
|
|
|
debug("i2c_write: chip=0x%x, addr=0x%x, len=0x%x\n",
|
|
chip, addr, len);
|
|
bus = tegra_i2c_get_bus(adap);
|
|
if (!bus)
|
|
return 1;
|
|
if (!i2c_addr_ok(addr, alen)) {
|
|
debug("i2c_write: Bad address %x.%d.\n", addr, alen);
|
|
return 1;
|
|
}
|
|
for (offset = 0; offset < len; offset++) {
|
|
uchar data[alen + 1];
|
|
for (i = 0; i < alen; i++)
|
|
data[alen - i - 1] = (addr + offset) >> (8 * i);
|
|
data[alen] = buffer[offset];
|
|
if (i2c_write_data(bus, chip, data, alen + 1)) {
|
|
debug("i2c_write: error sending (0x%x)\n", addr);
|
|
return 1;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int tegra_i2c_get_dvc_bus_num(void)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < TEGRA_I2C_NUM_CONTROLLERS; i++) {
|
|
struct i2c_bus *bus = &i2c_controllers[i];
|
|
|
|
if (bus->inited && bus->is_dvc)
|
|
return i;
|
|
}
|
|
|
|
return -1;
|
|
}
|
|
|
|
/*
|
|
* Register soft i2c adapters
|
|
*/
|
|
U_BOOT_I2C_ADAP_COMPLETE(tegra0, tegra_i2c_init, tegra_i2c_probe,
|
|
tegra_i2c_read, tegra_i2c_write,
|
|
tegra_i2c_set_bus_speed, 100000, 0, 0)
|
|
U_BOOT_I2C_ADAP_COMPLETE(tegra1, tegra_i2c_init, tegra_i2c_probe,
|
|
tegra_i2c_read, tegra_i2c_write,
|
|
tegra_i2c_set_bus_speed, 100000, 0, 1)
|
|
U_BOOT_I2C_ADAP_COMPLETE(tegra2, tegra_i2c_init, tegra_i2c_probe,
|
|
tegra_i2c_read, tegra_i2c_write,
|
|
tegra_i2c_set_bus_speed, 100000, 0, 2)
|
|
U_BOOT_I2C_ADAP_COMPLETE(tegra3, tegra_i2c_init, tegra_i2c_probe,
|
|
tegra_i2c_read, tegra_i2c_write,
|
|
tegra_i2c_set_bus_speed, 100000, 0, 3)
|
|
|