upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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554 lines
13 KiB
554 lines
13 KiB
/*
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* i2c driver for Freescale i.MX series
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*
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* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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* (c) 2011 Marek Vasut <marek.vasut@gmail.com>
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*
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* Based on i2c-imx.c from linux kernel:
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* Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
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* Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
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* Copyright (C) 2007 RightHand Technologies, Inc.
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* Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
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*
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/errno.h>
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#include <asm/io.h>
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#include <i2c.h>
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#include <watchdog.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef I2C_QUIRK_REG
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struct mxc_i2c_regs {
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uint8_t iadr;
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uint8_t ifdr;
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uint8_t i2cr;
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uint8_t i2sr;
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uint8_t i2dr;
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};
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#else
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struct mxc_i2c_regs {
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uint32_t iadr;
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uint32_t ifdr;
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uint32_t i2cr;
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uint32_t i2sr;
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uint32_t i2dr;
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};
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#endif
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#define I2CR_IIEN (1 << 6)
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#define I2CR_MSTA (1 << 5)
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#define I2CR_MTX (1 << 4)
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#define I2CR_TX_NO_AK (1 << 3)
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#define I2CR_RSTA (1 << 2)
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#define I2SR_ICF (1 << 7)
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#define I2SR_IBB (1 << 5)
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#define I2SR_IAL (1 << 4)
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#define I2SR_IIF (1 << 1)
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#define I2SR_RX_NO_AK (1 << 0)
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#ifdef I2C_QUIRK_REG
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#define I2CR_IEN (0 << 7)
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#define I2CR_IDIS (1 << 7)
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#define I2SR_IIF_CLEAR (1 << 1)
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#else
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#define I2CR_IEN (1 << 7)
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#define I2CR_IDIS (0 << 7)
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#define I2SR_IIF_CLEAR (0 << 1)
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#endif
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#if defined(CONFIG_HARD_I2C) && !defined(CONFIG_SYS_I2C_BASE)
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#error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver"
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#endif
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#ifdef I2C_QUIRK_REG
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static u16 i2c_clk_div[60][2] = {
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{ 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
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{ 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
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{ 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
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{ 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
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{ 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
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{ 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
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{ 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
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{ 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
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{ 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
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{ 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
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{ 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
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{ 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
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{ 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
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{ 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
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{ 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
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};
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#else
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static u16 i2c_clk_div[50][2] = {
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{ 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
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{ 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
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{ 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
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{ 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
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{ 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
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{ 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
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{ 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
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{ 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
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{ 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
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{ 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
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{ 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
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{ 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
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{ 3072, 0x1E }, { 3840, 0x1F }
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};
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#endif
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#ifndef CONFIG_SYS_MXC_I2C1_SPEED
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#define CONFIG_SYS_MXC_I2C1_SPEED 100000
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#endif
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#ifndef CONFIG_SYS_MXC_I2C2_SPEED
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#define CONFIG_SYS_MXC_I2C2_SPEED 100000
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#endif
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#ifndef CONFIG_SYS_MXC_I2C3_SPEED
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#define CONFIG_SYS_MXC_I2C3_SPEED 100000
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#endif
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#ifndef CONFIG_SYS_MXC_I2C1_SLAVE
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#define CONFIG_SYS_MXC_I2C1_SLAVE 0
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#endif
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#ifndef CONFIG_SYS_MXC_I2C2_SLAVE
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#define CONFIG_SYS_MXC_I2C2_SLAVE 0
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#endif
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#ifndef CONFIG_SYS_MXC_I2C3_SLAVE
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#define CONFIG_SYS_MXC_I2C3_SLAVE 0
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#endif
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/*
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* Calculate and set proper clock divider
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*/
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static uint8_t i2c_imx_get_clk(unsigned int rate)
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{
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unsigned int i2c_clk_rate;
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unsigned int div;
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u8 clk_div;
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#if defined(CONFIG_MX31)
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struct clock_control_regs *sc_regs =
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(struct clock_control_regs *)CCM_BASE;
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/* start the required I2C clock */
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writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
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&sc_regs->cgr0);
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#endif
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/* Divider value calculation */
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i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK);
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div = (i2c_clk_rate + rate - 1) / rate;
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if (div < i2c_clk_div[0][0])
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clk_div = 0;
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else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
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clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
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else
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for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
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;
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/* Store divider value */
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return clk_div;
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}
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/*
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* Set I2C Bus speed
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*/
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static int bus_i2c_set_bus_speed(void *base, int speed)
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{
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struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;
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u8 clk_idx = i2c_imx_get_clk(speed);
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u8 idx = i2c_clk_div[clk_idx][1];
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/* Store divider value */
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writeb(idx, &i2c_regs->ifdr);
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/* Reset module */
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writeb(I2CR_IDIS, &i2c_regs->i2cr);
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writeb(0, &i2c_regs->i2sr);
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return 0;
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}
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#define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
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#define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
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#define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))
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static int wait_for_sr_state(struct mxc_i2c_regs *i2c_regs, unsigned state)
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{
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unsigned sr;
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ulong elapsed;
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ulong start_time = get_timer(0);
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for (;;) {
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sr = readb(&i2c_regs->i2sr);
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if (sr & I2SR_IAL) {
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#ifdef I2C_QUIRK_REG
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writeb(sr | I2SR_IAL, &i2c_regs->i2sr);
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#else
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writeb(sr & ~I2SR_IAL, &i2c_regs->i2sr);
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#endif
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printf("%s: Arbitration lost sr=%x cr=%x state=%x\n",
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__func__, sr, readb(&i2c_regs->i2cr), state);
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return -ERESTART;
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}
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if ((sr & (state >> 8)) == (unsigned char)state)
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return sr;
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WATCHDOG_RESET();
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elapsed = get_timer(start_time);
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if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */
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break;
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}
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printf("%s: failed sr=%x cr=%x state=%x\n", __func__,
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sr, readb(&i2c_regs->i2cr), state);
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return -ETIMEDOUT;
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}
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static int tx_byte(struct mxc_i2c_regs *i2c_regs, u8 byte)
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{
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int ret;
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writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
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writeb(byte, &i2c_regs->i2dr);
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ret = wait_for_sr_state(i2c_regs, ST_IIF);
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if (ret < 0)
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return ret;
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if (ret & I2SR_RX_NO_AK)
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return -ENODEV;
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return 0;
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}
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/*
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* Stop I2C transaction
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*/
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static void i2c_imx_stop(struct mxc_i2c_regs *i2c_regs)
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{
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int ret;
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unsigned int temp = readb(&i2c_regs->i2cr);
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temp &= ~(I2CR_MSTA | I2CR_MTX);
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writeb(temp, &i2c_regs->i2cr);
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ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE);
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if (ret < 0)
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printf("%s:trigger stop failed\n", __func__);
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}
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/*
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* Send start signal, chip address and
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* write register address
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*/
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static int i2c_init_transfer_(struct mxc_i2c_regs *i2c_regs,
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uchar chip, uint addr, int alen)
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{
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unsigned int temp;
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int ret;
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/* Enable I2C controller */
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#ifdef I2C_QUIRK_REG
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if (readb(&i2c_regs->i2cr) & I2CR_IDIS) {
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#else
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if (!(readb(&i2c_regs->i2cr) & I2CR_IEN)) {
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#endif
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writeb(I2CR_IEN, &i2c_regs->i2cr);
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/* Wait for controller to be stable */
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udelay(50);
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}
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if (readb(&i2c_regs->iadr) == (chip << 1))
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writeb((chip << 1) ^ 2, &i2c_regs->iadr);
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writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
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ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE);
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if (ret < 0)
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return ret;
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/* Start I2C transaction */
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temp = readb(&i2c_regs->i2cr);
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temp |= I2CR_MSTA;
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writeb(temp, &i2c_regs->i2cr);
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ret = wait_for_sr_state(i2c_regs, ST_BUS_BUSY);
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if (ret < 0)
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return ret;
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temp |= I2CR_MTX | I2CR_TX_NO_AK;
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writeb(temp, &i2c_regs->i2cr);
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/* write slave address */
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ret = tx_byte(i2c_regs, chip << 1);
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if (ret < 0)
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return ret;
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while (alen--) {
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ret = tx_byte(i2c_regs, (addr >> (alen * 8)) & 0xff);
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if (ret < 0)
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return ret;
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}
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return 0;
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}
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static int i2c_idle_bus(void *base);
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static int i2c_init_transfer(struct mxc_i2c_regs *i2c_regs,
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uchar chip, uint addr, int alen)
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{
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int retry;
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int ret;
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for (retry = 0; retry < 3; retry++) {
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ret = i2c_init_transfer_(i2c_regs, chip, addr, alen);
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if (ret >= 0)
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return 0;
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i2c_imx_stop(i2c_regs);
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if (ret == -ENODEV)
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return ret;
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printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip,
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retry);
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if (ret != -ERESTART)
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/* Disable controller */
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writeb(I2CR_IDIS, &i2c_regs->i2cr);
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udelay(100);
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if (i2c_idle_bus(i2c_regs) < 0)
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break;
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}
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printf("%s: give up i2c_regs=%p\n", __func__, i2c_regs);
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return ret;
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}
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/*
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* Read data from I2C device
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*/
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int bus_i2c_read(void *base, uchar chip, uint addr, int alen, uchar *buf,
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int len)
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{
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int ret;
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unsigned int temp;
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int i;
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struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;
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ret = i2c_init_transfer(i2c_regs, chip, addr, alen);
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if (ret < 0)
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return ret;
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temp = readb(&i2c_regs->i2cr);
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temp |= I2CR_RSTA;
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writeb(temp, &i2c_regs->i2cr);
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ret = tx_byte(i2c_regs, (chip << 1) | 1);
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if (ret < 0) {
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i2c_imx_stop(i2c_regs);
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return ret;
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}
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/* setup bus to read data */
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temp = readb(&i2c_regs->i2cr);
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temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
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if (len == 1)
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temp |= I2CR_TX_NO_AK;
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writeb(temp, &i2c_regs->i2cr);
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writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
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readb(&i2c_regs->i2dr); /* dummy read to clear ICF */
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/* read data */
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for (i = 0; i < len; i++) {
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ret = wait_for_sr_state(i2c_regs, ST_IIF);
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if (ret < 0) {
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i2c_imx_stop(i2c_regs);
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return ret;
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}
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/*
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* It must generate STOP before read I2DR to prevent
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* controller from generating another clock cycle
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*/
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if (i == (len - 1)) {
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i2c_imx_stop(i2c_regs);
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} else if (i == (len - 2)) {
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temp = readb(&i2c_regs->i2cr);
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temp |= I2CR_TX_NO_AK;
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writeb(temp, &i2c_regs->i2cr);
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}
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writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
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buf[i] = readb(&i2c_regs->i2dr);
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}
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i2c_imx_stop(i2c_regs);
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return 0;
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}
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/*
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* Write data to I2C device
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*/
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int bus_i2c_write(void *base, uchar chip, uint addr, int alen,
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const uchar *buf, int len)
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{
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int ret;
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int i;
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struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;
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ret = i2c_init_transfer(i2c_regs, chip, addr, alen);
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if (ret < 0)
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return ret;
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for (i = 0; i < len; i++) {
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ret = tx_byte(i2c_regs, buf[i]);
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if (ret < 0)
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break;
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}
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i2c_imx_stop(i2c_regs);
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return ret;
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}
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struct i2c_parms {
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void *base;
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void *idle_bus_data;
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int (*idle_bus_fn)(void *p);
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};
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struct sram_data {
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unsigned curr_i2c_bus;
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struct i2c_parms i2c_data[3];
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};
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static void * const i2c_bases[] = {
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#if defined(CONFIG_MX25)
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(void *)IMX_I2C_BASE,
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(void *)IMX_I2C2_BASE,
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(void *)IMX_I2C3_BASE
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#elif defined(CONFIG_MX27)
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(void *)IMX_I2C1_BASE,
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(void *)IMX_I2C2_BASE
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#elif defined(CONFIG_MX31) || defined(CONFIG_MX35) || \
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defined(CONFIG_MX51) || defined(CONFIG_MX53) || \
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defined(CONFIG_MX6)
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(void *)I2C1_BASE_ADDR,
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(void *)I2C2_BASE_ADDR,
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(void *)I2C3_BASE_ADDR
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#elif defined(CONFIG_VF610)
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(void *)I2C0_BASE_ADDR
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#elif defined(CONFIG_FSL_LSCH3)
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(void *)I2C1_BASE_ADDR,
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(void *)I2C2_BASE_ADDR,
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(void *)I2C3_BASE_ADDR,
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(void *)I2C4_BASE_ADDR
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#else
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#error "architecture not supported"
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#endif
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};
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void *i2c_get_base(struct i2c_adapter *adap)
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{
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return i2c_bases[adap->hwadapnr];
|
|
}
|
|
|
|
static struct i2c_parms *i2c_get_parms(void *base)
|
|
{
|
|
struct sram_data *srdata = (void *)gd->srdata;
|
|
int i = 0;
|
|
struct i2c_parms *p = srdata->i2c_data;
|
|
while (i < ARRAY_SIZE(srdata->i2c_data)) {
|
|
if (p->base == base)
|
|
return p;
|
|
p++;
|
|
i++;
|
|
}
|
|
printf("Invalid I2C base: %p\n", base);
|
|
return NULL;
|
|
}
|
|
|
|
static int i2c_idle_bus(void *base)
|
|
{
|
|
struct i2c_parms *p = i2c_get_parms(base);
|
|
if (p && p->idle_bus_fn)
|
|
return p->idle_bus_fn(p->idle_bus_data);
|
|
return 0;
|
|
}
|
|
|
|
static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip,
|
|
uint addr, int alen, uint8_t *buffer,
|
|
int len)
|
|
{
|
|
return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len);
|
|
}
|
|
|
|
static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip,
|
|
uint addr, int alen, uint8_t *buffer,
|
|
int len)
|
|
{
|
|
return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len);
|
|
}
|
|
|
|
/*
|
|
* Test if a chip at a given address responds (probe the chip)
|
|
*/
|
|
static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
|
|
{
|
|
return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0);
|
|
}
|
|
|
|
void bus_i2c_init(void *base, int speed, int unused,
|
|
int (*idle_bus_fn)(void *p), void *idle_bus_data)
|
|
{
|
|
struct sram_data *srdata = (void *)gd->srdata;
|
|
int i = 0;
|
|
struct i2c_parms *p = srdata->i2c_data;
|
|
if (!base)
|
|
return;
|
|
for (;;) {
|
|
if (!p->base || (p->base == base)) {
|
|
p->base = base;
|
|
if (idle_bus_fn) {
|
|
p->idle_bus_fn = idle_bus_fn;
|
|
p->idle_bus_data = idle_bus_data;
|
|
}
|
|
break;
|
|
}
|
|
p++;
|
|
i++;
|
|
if (i >= ARRAY_SIZE(srdata->i2c_data))
|
|
return;
|
|
}
|
|
bus_i2c_set_bus_speed(base, speed);
|
|
}
|
|
|
|
/*
|
|
* Init I2C Bus
|
|
*/
|
|
static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
|
|
{
|
|
bus_i2c_init(i2c_get_base(adap), speed, slaveaddr, NULL, NULL);
|
|
}
|
|
|
|
/*
|
|
* Set I2C Speed
|
|
*/
|
|
static uint mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
|
|
{
|
|
return bus_i2c_set_bus_speed(i2c_get_base(adap), speed);
|
|
}
|
|
|
|
/*
|
|
* Register mxc i2c adapters
|
|
*/
|
|
U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe,
|
|
mxc_i2c_read, mxc_i2c_write,
|
|
mxc_i2c_set_bus_speed,
|
|
CONFIG_SYS_MXC_I2C1_SPEED,
|
|
CONFIG_SYS_MXC_I2C1_SLAVE, 0)
|
|
U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
|
|
mxc_i2c_read, mxc_i2c_write,
|
|
mxc_i2c_set_bus_speed,
|
|
CONFIG_SYS_MXC_I2C2_SPEED,
|
|
CONFIG_SYS_MXC_I2C2_SLAVE, 1)
|
|
#if defined(CONFIG_MX31) || defined(CONFIG_MX35) ||\
|
|
defined(CONFIG_MX51) || defined(CONFIG_MX53) ||\
|
|
defined(CONFIG_MX6)
|
|
U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
|
|
mxc_i2c_read, mxc_i2c_write,
|
|
mxc_i2c_set_bus_speed,
|
|
CONFIG_SYS_MXC_I2C3_SPEED,
|
|
CONFIG_SYS_MXC_I2C3_SLAVE, 2)
|
|
#endif
|
|
|