upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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757 lines
18 KiB
757 lines
18 KiB
/*
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* Copyright (C) 2005-2006 Atmel Corporation
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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/*
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* The u-boot networking stack is a little weird. It seems like the
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* networking core allocates receive buffers up front without any
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* regard to the hardware that's supposed to actually receive those
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* packets.
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*
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* The MACB receives packets into 128-byte receive buffers, so the
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* buffers allocated by the core isn't very practical to use. We'll
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* allocate our own, but we need one such buffer in case a packet
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* wraps around the DMA ring so that we have to copy it.
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*
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* Therefore, define CONFIG_SYS_RX_ETH_BUFFER to 1 in the board-specific
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* configuration header. This way, the core allocates one RX buffer
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* and one TX buffer, each of which can hold a ethernet packet of
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* maximum size.
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*
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* For some reason, the networking core unconditionally specifies a
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* 32-byte packet "alignment" (which really should be called
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* "padding"). MACB shouldn't need that, but we'll refrain from any
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* core modifications here...
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*/
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#include <net.h>
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#include <netdev.h>
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#include <malloc.h>
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#include <miiphy.h>
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#include <linux/mii.h>
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#include <asm/io.h>
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#include <asm/dma-mapping.h>
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#include <asm/arch/clk.h>
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#include <asm-generic/errno.h>
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#include "macb.h"
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#define MACB_RX_BUFFER_SIZE 4096
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#define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128)
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#define MACB_TX_RING_SIZE 16
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#define MACB_TX_TIMEOUT 1000
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#define MACB_AUTONEG_TIMEOUT 5000000
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struct macb_dma_desc {
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u32 addr;
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u32 ctrl;
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};
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#define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc))
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#define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE))
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#define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
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#define RXADDR_USED 0x00000001
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#define RXADDR_WRAP 0x00000002
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#define RXBUF_FRMLEN_MASK 0x00000fff
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#define RXBUF_FRAME_START 0x00004000
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#define RXBUF_FRAME_END 0x00008000
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#define RXBUF_TYPEID_MATCH 0x00400000
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#define RXBUF_ADDR4_MATCH 0x00800000
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#define RXBUF_ADDR3_MATCH 0x01000000
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#define RXBUF_ADDR2_MATCH 0x02000000
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#define RXBUF_ADDR1_MATCH 0x04000000
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#define RXBUF_BROADCAST 0x80000000
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#define TXBUF_FRMLEN_MASK 0x000007ff
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#define TXBUF_FRAME_END 0x00008000
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#define TXBUF_NOCRC 0x00010000
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#define TXBUF_EXHAUSTED 0x08000000
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#define TXBUF_UNDERRUN 0x10000000
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#define TXBUF_MAXRETRY 0x20000000
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#define TXBUF_WRAP 0x40000000
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#define TXBUF_USED 0x80000000
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struct macb_device {
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void *regs;
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unsigned int rx_tail;
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unsigned int tx_head;
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unsigned int tx_tail;
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void *rx_buffer;
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void *tx_buffer;
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struct macb_dma_desc *rx_ring;
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struct macb_dma_desc *tx_ring;
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unsigned long rx_buffer_dma;
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unsigned long rx_ring_dma;
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unsigned long tx_ring_dma;
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const struct device *dev;
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struct eth_device netdev;
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unsigned short phy_addr;
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struct mii_dev *bus;
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};
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#define to_macb(_nd) container_of(_nd, struct macb_device, netdev)
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static int macb_is_gem(struct macb_device *macb)
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{
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return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) == 0x2;
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}
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static void macb_mdio_write(struct macb_device *macb, u8 reg, u16 value)
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{
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unsigned long netctl;
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unsigned long netstat;
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unsigned long frame;
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netctl = macb_readl(macb, NCR);
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netctl |= MACB_BIT(MPE);
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macb_writel(macb, NCR, netctl);
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frame = (MACB_BF(SOF, 1)
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| MACB_BF(RW, 1)
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| MACB_BF(PHYA, macb->phy_addr)
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| MACB_BF(REGA, reg)
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| MACB_BF(CODE, 2)
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| MACB_BF(DATA, value));
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macb_writel(macb, MAN, frame);
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do {
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netstat = macb_readl(macb, NSR);
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} while (!(netstat & MACB_BIT(IDLE)));
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netctl = macb_readl(macb, NCR);
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netctl &= ~MACB_BIT(MPE);
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macb_writel(macb, NCR, netctl);
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}
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static u16 macb_mdio_read(struct macb_device *macb, u8 reg)
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{
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unsigned long netctl;
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unsigned long netstat;
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unsigned long frame;
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netctl = macb_readl(macb, NCR);
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netctl |= MACB_BIT(MPE);
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macb_writel(macb, NCR, netctl);
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frame = (MACB_BF(SOF, 1)
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| MACB_BF(RW, 2)
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| MACB_BF(PHYA, macb->phy_addr)
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| MACB_BF(REGA, reg)
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| MACB_BF(CODE, 2));
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macb_writel(macb, MAN, frame);
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do {
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netstat = macb_readl(macb, NSR);
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} while (!(netstat & MACB_BIT(IDLE)));
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frame = macb_readl(macb, MAN);
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netctl = macb_readl(macb, NCR);
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netctl &= ~MACB_BIT(MPE);
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macb_writel(macb, NCR, netctl);
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return MACB_BFEXT(DATA, frame);
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}
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void __weak arch_get_mdio_control(const char *name)
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{
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return;
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}
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#if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
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int macb_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value)
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{
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struct eth_device *dev = eth_get_dev_by_name(devname);
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struct macb_device *macb = to_macb(dev);
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if (macb->phy_addr != phy_adr)
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return -1;
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arch_get_mdio_control(devname);
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*value = macb_mdio_read(macb, reg);
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return 0;
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}
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int macb_miiphy_write(const char *devname, u8 phy_adr, u8 reg, u16 value)
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{
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struct eth_device *dev = eth_get_dev_by_name(devname);
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struct macb_device *macb = to_macb(dev);
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if (macb->phy_addr != phy_adr)
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return -1;
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arch_get_mdio_control(devname);
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macb_mdio_write(macb, reg, value);
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return 0;
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}
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#endif
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#define RX 1
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#define TX 0
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static inline void macb_invalidate_ring_desc(struct macb_device *macb, bool rx)
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{
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if (rx)
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invalidate_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma +
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MACB_RX_DMA_DESC_SIZE);
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else
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invalidate_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma +
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MACB_TX_DMA_DESC_SIZE);
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}
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static inline void macb_flush_ring_desc(struct macb_device *macb, bool rx)
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{
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if (rx)
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flush_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma +
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MACB_RX_DMA_DESC_SIZE);
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else
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flush_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma +
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MACB_TX_DMA_DESC_SIZE);
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}
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static inline void macb_flush_rx_buffer(struct macb_device *macb)
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{
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flush_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
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MACB_RX_BUFFER_SIZE);
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}
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static inline void macb_invalidate_rx_buffer(struct macb_device *macb)
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{
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invalidate_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
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MACB_RX_BUFFER_SIZE);
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}
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#if defined(CONFIG_CMD_NET)
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static int macb_send(struct eth_device *netdev, void *packet, int length)
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{
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struct macb_device *macb = to_macb(netdev);
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unsigned long paddr, ctrl;
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unsigned int tx_head = macb->tx_head;
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int i;
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paddr = dma_map_single(packet, length, DMA_TO_DEVICE);
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ctrl = length & TXBUF_FRMLEN_MASK;
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ctrl |= TXBUF_FRAME_END;
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if (tx_head == (MACB_TX_RING_SIZE - 1)) {
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ctrl |= TXBUF_WRAP;
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macb->tx_head = 0;
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} else {
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macb->tx_head++;
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}
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macb->tx_ring[tx_head].ctrl = ctrl;
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macb->tx_ring[tx_head].addr = paddr;
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barrier();
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macb_flush_ring_desc(macb, TX);
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/* Do we need check paddr and length is dcache line aligned? */
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flush_dcache_range(paddr, paddr + length);
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macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
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/*
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* I guess this is necessary because the networking core may
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* re-use the transmit buffer as soon as we return...
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*/
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for (i = 0; i <= MACB_TX_TIMEOUT; i++) {
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barrier();
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macb_invalidate_ring_desc(macb, TX);
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ctrl = macb->tx_ring[tx_head].ctrl;
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if (ctrl & TXBUF_USED)
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break;
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udelay(1);
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}
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dma_unmap_single(packet, length, paddr);
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if (i <= MACB_TX_TIMEOUT) {
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if (ctrl & TXBUF_UNDERRUN)
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printf("%s: TX underrun\n", netdev->name);
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if (ctrl & TXBUF_EXHAUSTED)
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printf("%s: TX buffers exhausted in mid frame\n",
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netdev->name);
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} else {
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printf("%s: TX timeout\n", netdev->name);
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}
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/* No one cares anyway */
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return 0;
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}
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static void reclaim_rx_buffers(struct macb_device *macb,
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unsigned int new_tail)
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{
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unsigned int i;
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i = macb->rx_tail;
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macb_invalidate_ring_desc(macb, RX);
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while (i > new_tail) {
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macb->rx_ring[i].addr &= ~RXADDR_USED;
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i++;
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if (i > MACB_RX_RING_SIZE)
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i = 0;
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}
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while (i < new_tail) {
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macb->rx_ring[i].addr &= ~RXADDR_USED;
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i++;
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}
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barrier();
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macb_flush_ring_desc(macb, RX);
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macb->rx_tail = new_tail;
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}
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static int macb_recv(struct eth_device *netdev)
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{
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struct macb_device *macb = to_macb(netdev);
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unsigned int rx_tail = macb->rx_tail;
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void *buffer;
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int length;
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int wrapped = 0;
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u32 status;
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for (;;) {
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macb_invalidate_ring_desc(macb, RX);
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if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED))
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return -1;
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status = macb->rx_ring[rx_tail].ctrl;
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if (status & RXBUF_FRAME_START) {
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if (rx_tail != macb->rx_tail)
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reclaim_rx_buffers(macb, rx_tail);
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wrapped = 0;
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}
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if (status & RXBUF_FRAME_END) {
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buffer = macb->rx_buffer + 128 * macb->rx_tail;
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length = status & RXBUF_FRMLEN_MASK;
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macb_invalidate_rx_buffer(macb);
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if (wrapped) {
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unsigned int headlen, taillen;
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headlen = 128 * (MACB_RX_RING_SIZE
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- macb->rx_tail);
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taillen = length - headlen;
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memcpy((void *)NetRxPackets[0],
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buffer, headlen);
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memcpy((void *)NetRxPackets[0] + headlen,
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macb->rx_buffer, taillen);
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buffer = (void *)NetRxPackets[0];
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}
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NetReceive(buffer, length);
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if (++rx_tail >= MACB_RX_RING_SIZE)
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rx_tail = 0;
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reclaim_rx_buffers(macb, rx_tail);
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} else {
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if (++rx_tail >= MACB_RX_RING_SIZE) {
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wrapped = 1;
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rx_tail = 0;
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}
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}
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barrier();
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}
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return 0;
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}
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static void macb_phy_reset(struct macb_device *macb)
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{
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struct eth_device *netdev = &macb->netdev;
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int i;
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u16 status, adv;
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adv = ADVERTISE_CSMA | ADVERTISE_ALL;
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macb_mdio_write(macb, MII_ADVERTISE, adv);
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printf("%s: Starting autonegotiation...\n", netdev->name);
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macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE
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| BMCR_ANRESTART));
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for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
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status = macb_mdio_read(macb, MII_BMSR);
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if (status & BMSR_ANEGCOMPLETE)
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break;
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udelay(100);
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}
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if (status & BMSR_ANEGCOMPLETE)
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printf("%s: Autonegotiation complete\n", netdev->name);
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else
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printf("%s: Autonegotiation timed out (status=0x%04x)\n",
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netdev->name, status);
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}
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#ifdef CONFIG_MACB_SEARCH_PHY
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static int macb_phy_find(struct macb_device *macb)
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{
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int i;
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u16 phy_id;
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/* Search for PHY... */
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for (i = 0; i < 32; i++) {
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macb->phy_addr = i;
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phy_id = macb_mdio_read(macb, MII_PHYSID1);
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if (phy_id != 0xffff) {
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printf("%s: PHY present at %d\n", macb->netdev.name, i);
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return 1;
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}
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}
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/* PHY isn't up to snuff */
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printf("%s: PHY not found\n", macb->netdev.name);
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return 0;
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}
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#endif /* CONFIG_MACB_SEARCH_PHY */
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static int macb_phy_init(struct macb_device *macb)
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{
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struct eth_device *netdev = &macb->netdev;
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#ifdef CONFIG_PHYLIB
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struct phy_device *phydev;
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#endif
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u32 ncfgr;
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u16 phy_id, status, adv, lpa;
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int media, speed, duplex;
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int i;
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arch_get_mdio_control(netdev->name);
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#ifdef CONFIG_MACB_SEARCH_PHY
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/* Auto-detect phy_addr */
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if (!macb_phy_find(macb))
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return 0;
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#endif /* CONFIG_MACB_SEARCH_PHY */
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/* Check if the PHY is up to snuff... */
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phy_id = macb_mdio_read(macb, MII_PHYSID1);
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if (phy_id == 0xffff) {
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printf("%s: No PHY present\n", netdev->name);
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return 0;
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}
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#ifdef CONFIG_PHYLIB
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/* need to consider other phy interface mode */
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phydev = phy_connect(macb->bus, macb->phy_addr, netdev,
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PHY_INTERFACE_MODE_RGMII);
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if (!phydev) {
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printf("phy_connect failed\n");
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return -ENODEV;
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}
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phy_config(phydev);
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#endif
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status = macb_mdio_read(macb, MII_BMSR);
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if (!(status & BMSR_LSTATUS)) {
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/* Try to re-negotiate if we don't have link already. */
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macb_phy_reset(macb);
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for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
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status = macb_mdio_read(macb, MII_BMSR);
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if (status & BMSR_LSTATUS)
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break;
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udelay(100);
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}
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}
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if (!(status & BMSR_LSTATUS)) {
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printf("%s: link down (status: 0x%04x)\n",
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netdev->name, status);
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return 0;
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}
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/* First check for GMAC */
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if (macb_is_gem(macb)) {
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lpa = macb_mdio_read(macb, MII_STAT1000);
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if (lpa & (1 << 11)) {
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speed = 1000;
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duplex = 1;
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} else {
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if (lpa & (1 << 10)) {
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speed = 1000;
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duplex = 1;
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} else {
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speed = 0;
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}
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}
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if (speed == 1000) {
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printf("%s: link up, %dMbps %s-duplex (lpa: 0x%04x)\n",
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netdev->name,
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speed,
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duplex ? "full" : "half",
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lpa);
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ncfgr = macb_readl(macb, NCFGR);
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ncfgr &= ~(GEM_BIT(GBE) | MACB_BIT(SPD) | MACB_BIT(FD));
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if (speed)
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ncfgr |= GEM_BIT(GBE);
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if (duplex)
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ncfgr |= MACB_BIT(FD);
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|
macb_writel(macb, NCFGR, ncfgr);
|
|
|
|
return 1;
|
|
}
|
|
}
|
|
|
|
/* fall back for EMAC checking */
|
|
adv = macb_mdio_read(macb, MII_ADVERTISE);
|
|
lpa = macb_mdio_read(macb, MII_LPA);
|
|
media = mii_nway_result(lpa & adv);
|
|
speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
|
|
? 1 : 0);
|
|
duplex = (media & ADVERTISE_FULL) ? 1 : 0;
|
|
printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
|
|
netdev->name,
|
|
speed ? "100" : "10",
|
|
duplex ? "full" : "half",
|
|
lpa);
|
|
|
|
ncfgr = macb_readl(macb, NCFGR);
|
|
ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
|
|
if (speed)
|
|
ncfgr |= MACB_BIT(SPD);
|
|
if (duplex)
|
|
ncfgr |= MACB_BIT(FD);
|
|
macb_writel(macb, NCFGR, ncfgr);
|
|
|
|
return 1;
|
|
}
|
|
|
|
static int macb_init(struct eth_device *netdev, bd_t *bd)
|
|
{
|
|
struct macb_device *macb = to_macb(netdev);
|
|
unsigned long paddr;
|
|
int i;
|
|
|
|
/*
|
|
* macb_halt should have been called at some point before now,
|
|
* so we'll assume the controller is idle.
|
|
*/
|
|
|
|
/* initialize DMA descriptors */
|
|
paddr = macb->rx_buffer_dma;
|
|
for (i = 0; i < MACB_RX_RING_SIZE; i++) {
|
|
if (i == (MACB_RX_RING_SIZE - 1))
|
|
paddr |= RXADDR_WRAP;
|
|
macb->rx_ring[i].addr = paddr;
|
|
macb->rx_ring[i].ctrl = 0;
|
|
paddr += 128;
|
|
}
|
|
macb_flush_ring_desc(macb, RX);
|
|
macb_flush_rx_buffer(macb);
|
|
|
|
for (i = 0; i < MACB_TX_RING_SIZE; i++) {
|
|
macb->tx_ring[i].addr = 0;
|
|
if (i == (MACB_TX_RING_SIZE - 1))
|
|
macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP;
|
|
else
|
|
macb->tx_ring[i].ctrl = TXBUF_USED;
|
|
}
|
|
macb_flush_ring_desc(macb, TX);
|
|
|
|
macb->rx_tail = 0;
|
|
macb->tx_head = 0;
|
|
macb->tx_tail = 0;
|
|
|
|
macb_writel(macb, RBQP, macb->rx_ring_dma);
|
|
macb_writel(macb, TBQP, macb->tx_ring_dma);
|
|
|
|
if (macb_is_gem(macb)) {
|
|
#ifdef CONFIG_RGMII
|
|
gem_writel(macb, UR, GEM_BIT(RGMII));
|
|
#else
|
|
gem_writel(macb, UR, 0);
|
|
#endif
|
|
} else {
|
|
/* choose RMII or MII mode. This depends on the board */
|
|
#ifdef CONFIG_RMII
|
|
#ifdef CONFIG_AT91FAMILY
|
|
macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));
|
|
#else
|
|
macb_writel(macb, USRIO, 0);
|
|
#endif
|
|
#else
|
|
#ifdef CONFIG_AT91FAMILY
|
|
macb_writel(macb, USRIO, MACB_BIT(CLKEN));
|
|
#else
|
|
macb_writel(macb, USRIO, MACB_BIT(MII));
|
|
#endif
|
|
#endif /* CONFIG_RMII */
|
|
}
|
|
|
|
if (!macb_phy_init(macb))
|
|
return -1;
|
|
|
|
/* Enable TX and RX */
|
|
macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void macb_halt(struct eth_device *netdev)
|
|
{
|
|
struct macb_device *macb = to_macb(netdev);
|
|
u32 ncr, tsr;
|
|
|
|
/* Halt the controller and wait for any ongoing transmission to end. */
|
|
ncr = macb_readl(macb, NCR);
|
|
ncr |= MACB_BIT(THALT);
|
|
macb_writel(macb, NCR, ncr);
|
|
|
|
do {
|
|
tsr = macb_readl(macb, TSR);
|
|
} while (tsr & MACB_BIT(TGO));
|
|
|
|
/* Disable TX and RX, and clear statistics */
|
|
macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
|
|
}
|
|
|
|
static int macb_write_hwaddr(struct eth_device *dev)
|
|
{
|
|
struct macb_device *macb = to_macb(dev);
|
|
u32 hwaddr_bottom;
|
|
u16 hwaddr_top;
|
|
|
|
/* set hardware address */
|
|
hwaddr_bottom = dev->enetaddr[0] | dev->enetaddr[1] << 8 |
|
|
dev->enetaddr[2] << 16 | dev->enetaddr[3] << 24;
|
|
macb_writel(macb, SA1B, hwaddr_bottom);
|
|
hwaddr_top = dev->enetaddr[4] | dev->enetaddr[5] << 8;
|
|
macb_writel(macb, SA1T, hwaddr_top);
|
|
return 0;
|
|
}
|
|
|
|
static u32 macb_mdc_clk_div(int id, struct macb_device *macb)
|
|
{
|
|
u32 config;
|
|
unsigned long macb_hz = get_macb_pclk_rate(id);
|
|
|
|
if (macb_hz < 20000000)
|
|
config = MACB_BF(CLK, MACB_CLK_DIV8);
|
|
else if (macb_hz < 40000000)
|
|
config = MACB_BF(CLK, MACB_CLK_DIV16);
|
|
else if (macb_hz < 80000000)
|
|
config = MACB_BF(CLK, MACB_CLK_DIV32);
|
|
else
|
|
config = MACB_BF(CLK, MACB_CLK_DIV64);
|
|
|
|
return config;
|
|
}
|
|
|
|
static u32 gem_mdc_clk_div(int id, struct macb_device *macb)
|
|
{
|
|
u32 config;
|
|
unsigned long macb_hz = get_macb_pclk_rate(id);
|
|
|
|
if (macb_hz < 20000000)
|
|
config = GEM_BF(CLK, GEM_CLK_DIV8);
|
|
else if (macb_hz < 40000000)
|
|
config = GEM_BF(CLK, GEM_CLK_DIV16);
|
|
else if (macb_hz < 80000000)
|
|
config = GEM_BF(CLK, GEM_CLK_DIV32);
|
|
else if (macb_hz < 120000000)
|
|
config = GEM_BF(CLK, GEM_CLK_DIV48);
|
|
else if (macb_hz < 160000000)
|
|
config = GEM_BF(CLK, GEM_CLK_DIV64);
|
|
else
|
|
config = GEM_BF(CLK, GEM_CLK_DIV96);
|
|
|
|
return config;
|
|
}
|
|
|
|
/*
|
|
* Get the DMA bus width field of the network configuration register that we
|
|
* should program. We find the width from decoding the design configuration
|
|
* register to find the maximum supported data bus width.
|
|
*/
|
|
static u32 macb_dbw(struct macb_device *macb)
|
|
{
|
|
switch (GEM_BFEXT(DBWDEF, gem_readl(macb, DCFG1))) {
|
|
case 4:
|
|
return GEM_BF(DBW, GEM_DBW128);
|
|
case 2:
|
|
return GEM_BF(DBW, GEM_DBW64);
|
|
case 1:
|
|
default:
|
|
return GEM_BF(DBW, GEM_DBW32);
|
|
}
|
|
}
|
|
|
|
int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
|
|
{
|
|
struct macb_device *macb;
|
|
struct eth_device *netdev;
|
|
u32 ncfgr;
|
|
|
|
macb = malloc(sizeof(struct macb_device));
|
|
if (!macb) {
|
|
printf("Error: Failed to allocate memory for MACB%d\n", id);
|
|
return -1;
|
|
}
|
|
memset(macb, 0, sizeof(struct macb_device));
|
|
|
|
netdev = &macb->netdev;
|
|
|
|
macb->rx_buffer = dma_alloc_coherent(MACB_RX_BUFFER_SIZE,
|
|
&macb->rx_buffer_dma);
|
|
macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE,
|
|
&macb->rx_ring_dma);
|
|
macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE,
|
|
&macb->tx_ring_dma);
|
|
|
|
/* TODO: we need check the rx/tx_ring_dma is dcache line aligned */
|
|
|
|
macb->regs = regs;
|
|
macb->phy_addr = phy_addr;
|
|
|
|
if (macb_is_gem(macb))
|
|
sprintf(netdev->name, "gmac%d", id);
|
|
else
|
|
sprintf(netdev->name, "macb%d", id);
|
|
|
|
netdev->init = macb_init;
|
|
netdev->halt = macb_halt;
|
|
netdev->send = macb_send;
|
|
netdev->recv = macb_recv;
|
|
netdev->write_hwaddr = macb_write_hwaddr;
|
|
|
|
/*
|
|
* Do some basic initialization so that we at least can talk
|
|
* to the PHY
|
|
*/
|
|
if (macb_is_gem(macb)) {
|
|
ncfgr = gem_mdc_clk_div(id, macb);
|
|
ncfgr |= macb_dbw(macb);
|
|
} else {
|
|
ncfgr = macb_mdc_clk_div(id, macb);
|
|
}
|
|
|
|
macb_writel(macb, NCFGR, ncfgr);
|
|
|
|
eth_register(netdev);
|
|
|
|
#if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
|
|
miiphy_register(netdev->name, macb_miiphy_read, macb_miiphy_write);
|
|
macb->bus = miiphy_get_dev_by_name(netdev->name);
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
#endif
|
|
|