upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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335 lines
17 KiB
335 lines
17 KiB
/***********************************************************************
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*
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* Copyright 2003 by FS Forth-Systeme GmbH.
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* All rights reserved.
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*
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* $Id$
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* @Author: Markus Pietrek
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* @Descr: Defines the NS7520 ethernet registers.
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* Stick with the old ETH prefix names instead going to the
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* new EFE names in the manual.
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* NS7520_ETH_* refer to NS7520 Hardware
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* Reference/January 2003 [1]
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* PHY_LXT971_* refer to Intel LXT971 Datasheet
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* #249414 Rev. 02 [2]
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* Partly derived from netarm_eth_module.h
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*
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* Modified by Arthur Shipkowski <art@videon-central.com> from the
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* Linux version to be properly formatted for U-Boot (i.e. no C++ comments)
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*
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***********************************************************************/
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#ifndef FS_NS7520_ETH_H
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#define FS_NS7520_ETH_H
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#ifdef CONFIG_DRIVER_NS7520_ETHERNET
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#include "lxt971a.h"
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/* The port addresses */
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#define NS7520_ETH_MODULE_BASE (0xFF800000)
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#define get_eth_reg_addr(c) \
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((volatile unsigned int*) ( NS7520_ETH_MODULE_BASE+(unsigned int) (c)))
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#define NS7520_ETH_EGCR (0x0000) /* Ethernet Gen Control */
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#define NS7520_ETH_EGSR (0x0004) /* Ethernet Gen Status */
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#define NS7520_ETH_FIFO (0x0008) /* FIFO Data */
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#define NS7520_ETH_FIFOL (0x000C) /* FIFO Data Last */
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#define NS7520_ETH_ETSR (0x0010) /* Ethernet Transmit Status */
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#define NS7520_ETH_ERSR (0x0014) /* Ethernet Receive Status */
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#define NS7520_ETH_MAC1 (0x0400) /* MAC Config 1 */
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#define NS7520_ETH_MAC2 (0x0404) /* MAC Config 2 */
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#define NS7520_ETH_IPGT (0x0408) /* Back2Back InterPacket Gap */
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#define NS7520_ETH_IPGR (0x040C) /* non back2back InterPacket Gap */
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#define NS7520_ETH_CLRT (0x0410) /* Collision Window/Retry */
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#define NS7520_ETH_MAXF (0x0414) /* Maximum Frame Register */
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#define NS7520_ETH_SUPP (0x0418) /* PHY Support */
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#define NS7520_ETH_TEST (0x041C) /* Test Register */
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#define NS7520_ETH_MCFG (0x0420) /* MII Management Configuration */
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#define NS7520_ETH_MCMD (0x0424) /* MII Management Command */
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#define NS7520_ETH_MADR (0x0428) /* MII Management Address */
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#define NS7520_ETH_MWTD (0x042C) /* MII Management Write Data */
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#define NS7520_ETH_MRDD (0x0430) /* MII Management Read Data */
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#define NS7520_ETH_MIND (0x0434) /* MII Management Indicators */
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#define NS7520_ETH_SMII (0x0438) /* SMII Status Register */
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#define NS7520_ETH_SA1 (0x0440) /* Station Address 1 */
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#define NS7520_ETH_SA2 (0x0444) /* Station Address 2 */
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#define NS7520_ETH_SA3 (0x0448) /* Station Address 3 */
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#define NS7520_ETH_SAFR (0x05C0) /* Station Address Filter */
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#define NS7520_ETH_HT1 (0x05D0) /* Hash Table 1 */
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#define NS7520_ETH_HT2 (0x05D4) /* Hash Table 2 */
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#define NS7520_ETH_HT3 (0x05D8) /* Hash Table 3 */
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#define NS7520_ETH_HT4 (0x05DC) /* Hash Table 4 */
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/* EGCR Ethernet General Control Register Bit Fields*/
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#define NS7520_ETH_EGCR_ERX (0x80000000) /* Enable Receive FIFO */
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#define NS7520_ETH_EGCR_ERXDMA (0x40000000) /* Enable Receive DMA */
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#define NS7520_ETH_EGCR_ERXLNG (0x20000000) /* Accept Long packets */
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#define NS7520_ETH_EGCR_ERXSHT (0x10000000) /* Accept Short packets */
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#define NS7520_ETH_EGCR_ERXREG (0x08000000) /* Enable Receive Data Interrupt */
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#define NS7520_ETH_EGCR_ERFIFOH (0x04000000) /* Enable Receive Half-Full Int */
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#define NS7520_ETH_EGCR_ERXBR (0x02000000) /* Enable Receive buffer ready */
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#define NS7520_ETH_EGCR_ERXBAD (0x01000000) /* Accept bad receive packets */
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#define NS7520_ETH_EGCR_ETX (0x00800000) /* Enable Transmit FIFO */
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#define NS7520_ETH_EGCR_ETXDMA (0x00400000) /* Enable Transmit DMA */
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#define NS7520_ETH_EGCR_ETXWM_R (0x00300000) /* Enable Transmit FIFO mark Reserv */
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#define NS7520_ETH_EGCR_ETXWM_75 (0x00200000) /* Enable Transmit FIFO mark 75% */
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#define NS7520_ETH_EGCR_ETXWM_50 (0x00100000) /* Enable Transmit FIFO mark 50% */
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#define NS7520_ETH_EGCR_ETXWM_25 (0x00000000) /* Enable Transmit FIFO mark 25% */
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#define NS7520_ETH_EGCR_ETXREG (0x00080000) /* Enable Transmit Data Read Int */
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#define NS7520_ETH_EGCR_ETFIFOH (0x00040000) /* Enable Transmit Fifo Half Int */
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#define NS7520_ETH_EGCR_ETXBC (0x00020000) /* Enable Transmit Buffer Compl Int */
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#define NS7520_ETH_EGCR_EFULLD (0x00010000) /* Enable Full Duplex Operation */
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#define NS7520_ETH_EGCR_MODE_MA (0x0000C000) /* Mask */
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#define NS7520_ETH_EGCR_MODE_SEE (0x0000C000) /* 10 Mbps SEEQ ENDEC PHY */
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#define NS7520_ETH_EGCR_MODE_LEV (0x00008000) /* 10 Mbps Level1 ENDEC PHY */
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#define NS7520_ETH_EGCR_RES1 (0x00002000) /* Reserved */
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#define NS7520_ETH_EGCR_RXCINV (0x00001000) /* Invert the receive clock input */
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#define NS7520_ETH_EGCR_TXCINV (0x00000800) /* Invert the transmit clock input */
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#define NS7520_ETH_EGCR_PNA (0x00000400) /* pSOS pNA buffer */
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#define NS7520_ETH_EGCR_MAC_RES (0x00000200) /* MAC Software reset */
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#define NS7520_ETH_EGCR_ITXA (0x00000100) /* Insert Transmit Source Address */
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#define NS7520_ETH_EGCR_ENDEC_MA (0x000000FC) /* ENDEC media control bits */
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#define NS7520_ETH_EGCR_EXINT_MA (0x00000003) /* Mask */
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#define NS7520_ETH_EGCR_EXINT_RE (0x00000003) /* Reserved */
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#define NS7520_ETH_EGCR_EXINT_TP (0x00000002) /* TP-PMD Mode */
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#define NS7520_ETH_EGCR_EXINT_10 (0x00000001) /* 10-MBit Mode */
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#define NS7520_ETH_EGCR_EXINT_NO (0x00000000) /* MII normal operation */
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/* EGSR Ethernet General Status Register Bit Fields*/
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#define NS7520_ETH_EGSR_RES1 (0xC0000000) /* Reserved */
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#define NS7520_ETH_EGSR_RXFDB_MA (0x30000000) /* Receive FIFO mask */
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#define NS7520_ETH_EGSR_RXFDB_3 (0x30000000) /* Receive FIFO 3 bytes available */
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#define NS7520_ETH_EGSR_RXFDB_2 (0x20000000) /* Receive FIFO 2 bytes available */
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#define NS7520_ETH_EGCR_RXFDB_1 (0x10000000) /* Receive FIFO 1 Bytes available */
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#define NS7520_ETH_EGCR_RXFDB_4 (0x00000000) /* Receive FIFO 4 Bytes available */
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#define NS7520_ETH_EGSR_RXREGR (0x08000000) /* Receive Register Ready */
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#define NS7520_ETH_EGSR_RXFIFOH (0x04000000) /* Receive FIFO Half Full */
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#define NS7520_ETH_EGSR_RXBR (0x02000000) /* Receive Buffer Ready */
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#define NS7520_ETH_EGSR_RXSKIP (0x01000000) /* Receive Buffer Skip */
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#define NS7520_ETH_EGSR_RES2 (0x00F00000) /* Reserved */
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#define NS7520_ETH_EGSR_TXREGE (0x00080000) /* Transmit Register Empty */
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#define NS7520_ETH_EGSR_TXFIFOH (0x00040000) /* Transmit FIFO half empty */
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#define NS7520_ETH_EGSR_TXBC (0x00020000) /* Transmit buffer complete */
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#define NS7520_ETH_EGSR_TXFIFOE (0x00010000) /* Transmit FIFO empty */
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#define NS7520_ETH_EGSR_RXPINS (0x0000FC00) /* ENDEC Phy Status */
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#define NS7520_ETH_EGSR_RES3 (0x000003FF) /* Reserved */
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/* ETSR Ethernet Transmit Status Register Bit Fields*/
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#define NS7520_ETH_ETSR_RES1 (0xFFFF0000) /* Reserved */
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#define NS7520_ETH_ETSR_TXOK (0x00008000) /* Packet transmitted OK */
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#define NS7520_ETH_ETSR_TXBR (0x00004000) /* Broadcast packet transmitted */
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#define NS7520_ETH_ETSR_TXMC (0x00002000) /* Multicast packet transmitted */
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#define NS7520_ETH_ETSR_TXAL (0x00001000) /* Transmit abort - late collision */
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#define NS7520_ETH_ETSR_TXAED (0x00000800) /* Transmit abort - deferral */
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#define NS7520_ETH_ETSR_TXAEC (0x00000400) /* Transmit abort - exc collisions */
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#define NS7520_ETH_ETSR_TXAUR (0x00000200) /* Transmit abort - underrun */
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#define NS7520_ETH_ETSR_TXAJ (0x00000100) /* Transmit abort - jumbo */
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#define NS7520_ETH_ETSR_RES2 (0x00000080) /* Reserved */
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#define NS7520_ETH_ETSR_TXDEF (0x00000040) /* Transmit Packet Deferred */
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#define NS7520_ETH_ETSR_TXCRC (0x00000020) /* Transmit CRC error */
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#define NS7520_ETH_ETSR_RES3 (0x00000010) /* Reserved */
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#define NS7520_ETH_ETSR_TXCOLC (0x0000000F) /* Transmit Collision Count */
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/* ERSR Ethernet Receive Status Register Bit Fields*/
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#define NS7520_ETH_ERSR_RXSIZE (0xFFFF0000) /* Receive Buffer Size */
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#define NS7520_ETH_ERSR_RXCE (0x00008000) /* Receive Carrier Event */
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#define NS7520_ETH_ERSR_RXDV (0x00004000) /* Receive Data Violation Event */
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#define NS7520_ETH_ERSR_RXOK (0x00002000) /* Receive Packet OK */
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#define NS7520_ETH_ERSR_RXBR (0x00001000) /* Receive Broadcast Packet */
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#define NS7520_ETH_ERSR_RXMC (0x00000800) /* Receive Multicast Packet */
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#define NS7520_ETH_ERSR_RXCRC (0x00000400) /* Receive Packet has CRC error */
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#define NS7520_ETH_ERSR_RXDR (0x00000200) /* Receive Packet has dribble error */
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#define NS7520_ETH_ERSR_RXCV (0x00000100) /* Receive Packet code violation */
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#define NS7520_ETH_ERSR_RXLNG (0x00000080) /* Receive Packet too long */
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#define NS7520_ETH_ERSR_RXSHT (0x00000040) /* Receive Packet too short */
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#define NS7520_ETH_ERSR_ROVER (0x00000020) /* Recive overflow */
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#define NS7520_ETH_ERSR_RES (0x0000001F) /* Reserved */
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/* MAC1 MAC Configuration Register 1 Bit Fields*/
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#define NS7520_ETH_MAC1_RES1 (0xFFFF0000) /* Reserved */
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#define NS7520_ETH_MAC1_SRST (0x00008000) /* Soft Reset */
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#define NS7520_ETH_MAC1_SIMMRST (0x00004000) /* Simulation Reset */
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#define NS7520_ETH_MAC1_RES2 (0x00003000) /* Reserved */
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#define NS7520_ETH_MAC1_RPEMCSR (0x00000800) /* Reset PEMCS/RX */
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#define NS7520_ETH_MAC1_RPERFUN (0x00000400) /* Reset PERFUN */
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#define NS7520_ETH_MAC1_RPEMCST (0x00000200) /* Reset PEMCS/TX */
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#define NS7520_ETH_MAC1_RPETFUN (0x00000100) /* Reset PETFUN */
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#define NS7520_ETH_MAC1_RES3 (0x000000E0) /* Reserved */
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#define NS7520_ETH_MAC1_LOOPBK (0x00000010) /* Internal Loopback */
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#define NS7520_ETH_MAC1_TXFLOW (0x00000008) /* TX flow control */
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#define NS7520_ETH_MAC1_RXFLOW (0x00000004) /* RX flow control */
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#define NS7520_ETH_MAC1_PALLRX (0x00000002) /* Pass ALL receive frames */
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#define NS7520_ETH_MAC1_RXEN (0x00000001) /* Receive enable */
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/* MAC Configuration Register 2 Bit Fields*/
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#define NS7520_ETH_MAC2_RES1 (0xFFFF8000) /* Reserved */
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#define NS7520_ETH_MAC2_EDEFER (0x00004000) /* Excess Deferral */
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#define NS7520_ETH_MAC2_BACKP (0x00002000) /* Backpressure/NO back off */
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#define NS7520_ETH_MAC2_NOBO (0x00001000) /* No back off */
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#define NS7520_ETH_MAC2_RES2 (0x00000C00) /* Reserved */
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#define NS7520_ETH_MAC2_LONGP (0x00000200) /* Long Preable enforcement */
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#define NS7520_ETH_MAC2_PUREP (0x00000100) /* Pure preamble enforcement */
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#define NS7520_ETH_MAC2_AUTOP (0x00000080) /* Auto detect PAD enable */
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#define NS7520_ETH_MAC2_VLANP (0x00000040) /* VLAN pad enable */
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#define NS7520_ETH_MAC2_PADEN (0x00000020) /* PAD/CRC enable */
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#define NS7520_ETH_MAC2_CRCEN (0x00000010) /* CRC enable */
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#define NS7520_ETH_MAC2_DELCRC (0x00000008) /* Delayed CRC */
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#define NS7520_ETH_MAC2_HUGE (0x00000004) /* Huge frame enable */
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#define NS7520_ETH_MAC2_FLENC (0x00000002) /* Frame length checking */
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#define NS7520_ETH_MAC2_FULLD (0x00000001) /* Full duplex */
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/* IPGT Back-to-Back Inter-Packet-Gap Register Bit Fields*/
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#define NS7520_ETH_IPGT_RES (0xFFFFFF80) /* Reserved */
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#define NS7520_ETH_IPGT_IPGT (0x0000007F) /* Back-to-Back Interpacket Gap */
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/* IPGR Non Back-to-Back Inter-Packet-Gap Register Bit Fields*/
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#define NS7520_ETH_IPGR_RES1 (0xFFFF8000) /* Reserved */
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#define NS7520_ETH_IPGR_IPGR1 (0x00007F00) /* Non Back-to-back Interpacket Gap */
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#define NS7520_ETH_IPGR_RES2 (0x00000080) /* Reserved */
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#define NS7520_ETH_IPGR_IPGR2 (0x0000007F) /* Non back-to-back Interpacket Gap */
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/* CLRT Collision Windows/Collision Retry Register Bit Fields*/
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#define NS7520_ETH_CLRT_RES1 (0xFFFFC000) /* Reserved */
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#define NS7520_ETH_CLRT_CWIN (0x00003F00) /* Collision Windows */
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#define NS7520_ETH_CLRT_RES2 (0x000000F0) /* Reserved */
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#define NS7520_ETH_CLRT_RETX (0x0000000F) /* Retransmission maximum */
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/* MAXF Maximum Frame Register Bit Fields*/
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#define NS7520_ETH_MAXF_RES1 (0xFFFF0000) /* Reserved */
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#define NS7520_ETH_MAXF_MAXF (0x0000FFFF) /* Maximum frame length */
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/* SUPP PHY Support Register Bit Fields*/
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#define NS7520_ETH_SUPP_RES1 (0xFFFFFF00) /* Reserved */
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#define NS7520_ETH_SUPP_RPE100X (0x00000080) /* Reset PE100X module */
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#define NS7520_ETH_SUPP_FORCEQ (0x00000040) /* Force Quit */
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#define NS7520_ETH_SUPP_NOCIPH (0x00000020) /* No Cipher */
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#define NS7520_ETH_SUPP_DLINKF (0x00000010) /* Disable link fail */
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#define NS7520_ETH_SUPP_RPE10T (0x00000008) /* Reset PE10T module */
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#define NS7520_ETH_SUPP_RES2 (0x00000004) /* Reserved */
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#define NS7520_ETH_SUPP_JABBER (0x00000002) /* Enable Jabber protection */
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#define NS7520_ETH_SUPP_BITMODE (0x00000001) /* Bit Mode */
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/* TEST Register Bit Fields*/
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#define NS7520_ETH_TEST_RES1 (0xFFFFFFF8) /* Reserved */
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#define NS7520_ETH_TEST_TBACK (0x00000004) /* Test backpressure */
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#define NS7520_ETH_TEST_TPAUSE (0x00000002) /* Test Pause */
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#define NS7520_ETH_TEST_SPQ (0x00000001) /* Shortcut pause quanta */
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/* MCFG MII Management Configuration Register Bit Fields*/
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#define NS7520_ETH_MCFG_RES1 (0xFFFF0000) /* Reserved */
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#define NS7520_ETH_MCFG_RMIIM (0x00008000) /* Reset MII management */
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#define NS7520_ETH_MCFG_RES2 (0x00007FE0) /* Reserved */
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#define NS7520_ETH_MCFG_CLKS_MA (0x0000001C) /* Clock Select */
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#define NS7520_ETH_MCFG_CLKS_4 (0x00000004) /* Sysclk / 4 */
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#define NS7520_ETH_MCFG_CLKS_6 (0x00000008) /* Sysclk / 6 */
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#define NS7520_ETH_MCFG_CLKS_8 (0x0000000C) /* Sysclk / 8 */
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#define NS7520_ETH_MCFG_CLKS_10 (0x00000010) /* Sysclk / 10 */
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#define NS7520_ETH_MCFG_CLKS_14 (0x00000014) /* Sysclk / 14 */
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#define NS7520_ETH_MCFG_CLKS_20 (0x00000018) /* Sysclk / 20 */
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#define NS7520_ETH_MCFG_CLKS_28 (0x0000001C) /* Sysclk / 28 */
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#define NS7520_ETH_MCFG_SPRE (0x00000002) /* Suppress preamble */
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#define NS7520_ETH_MCFG_SCANI (0x00000001) /* Scan increment */
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/* MCMD MII Management Command Register Bit Fields*/
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#define NS7520_ETH_MCMD_RES1 (0xFFFFFFFC) /* Reserved */
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#define NS7520_ETH_MCMD_SCAN (0x00000002) /* Automatically Scan for Read Data */
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#define NS7520_ETH_MCMD_READ (0x00000001) /* Single scan for Read Data */
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/* MCMD MII Management Address Register Bit Fields*/
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#define NS7520_ETH_MADR_RES1 (0xFFFFE000) /* Reserved */
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#define NS7520_ETH_MADR_DADR (0x00001F00) /* MII PHY device address */
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#define NS7520_ETH_MADR_RES2 (0x000000E0) /* Reserved */
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#define NS7520_ETH_MADR_RADR (0x0000001F) /* MII PHY register address */
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/* MWTD MII Management Write Data Register Bit Fields*/
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#define NS7520_ETH_MWTD_RES1 (0xFFFF0000) /* Reserved */
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#define NS7520_ETH_MWTD_MWTD (0x0000FFFF) /* MII Write Data */
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/* MRRD MII Management Read Data Register Bit Fields*/
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#define NS7520_ETH_MRRD_RES1 (0xFFFF0000) /* Reserved */
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#define NS7520_ETH_MRRD_MRDD (0x0000FFFF) /* MII Read Data */
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/* MIND MII Management Indicators Register Bit Fields*/
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#define NS7520_ETH_MIND_RES1 (0xFFFFFFF8) /* Reserved */
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#define NS7520_ETH_MIND_NVALID (0x00000004) /* Read Data not valid */
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#define NS7520_ETH_MIND_SCAN (0x00000002) /* Automatically scan for read data */
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#define NS7520_ETH_MIND_BUSY (0x00000001) /* MII interface busy */
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/* SMII Status Register Bit Fields*/
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#define NS7520_ETH_SMII_RES1 (0xFFFFFFE0) /* Reserved */
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#define NS7520_ETH_SMII_CLASH (0x00000010) /* MAC-to-MAC with PHY */
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#define NS7520_ETH_SMII_JABBER (0x00000008) /* Jabber condition present */
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#define NS7520_ETH_SMII_LINK (0x00000004) /* Link OK */
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#define NS7520_ETH_SMII_DUPLEX (0x00000002) /* Full-duplex operation */
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#define NS7520_ETH_SMII_SPEED (0x00000001) /* 100 Mbps */
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/* SA1 Station Address 1 Register Bit Fields*/
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#define NS7520_ETH_SA1_RES1 (0xFFFF0000) /* Reserved */
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#define NS7520_ETH_SA1_OCTET1 (0x0000FF00) /* Station Address octet 1 */
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#define NS7520_ETH_SA1_OCTET2 (0x000000FF) /* Station Address octet 2 */
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/* SA2 Station Address 2 Register Bit Fields*/
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#define NS7520_ETH_SA2_RES1 (0xFFFF0000) /* Reserved */
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#define NS7520_ETH_SA2_OCTET3 (0x0000FF00) /* Station Address octet 3 */
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#define NS7520_ETH_SA2_OCTET4 (0x000000FF) /* Station Address octet 4 */
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/* SA3 Station Address 3 Register Bit Fields*/
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#define NS7520_ETH_SA3_RES1 (0xFFFF0000) /* Reserved */
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#define NS7520_ETH_SA3_OCTET5 (0x0000FF00) /* Station Address octet 5 */
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#define NS7520_ETH_SA3_OCTET6 (0x000000FF) /* Station Address octet 6 */
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/* SAFR Station Address Filter Register Bit Fields*/
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#define NS7520_ETH_SAFR_RES1 (0xFFFFFFF0) /* Reserved */
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#define NS7520_ETH_SAFR_PRO (0x00000008) /* Enable Promiscuous mode */
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#define NS7520_ETH_SAFR_PRM (0x00000004) /* Accept ALL multicast packets */
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#define NS7520_ETH_SAFR_PRA (0x00000002) /* Accept multicast packets table */
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#define NS7520_ETH_SAFR_BROAD (0x00000001) /* Accept ALL Broadcast packets */
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/* HT1 Hash Table 1 Register Bit Fields*/
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#define NS7520_ETH_HT1_RES1 (0xFFFF0000) /* Reserved */
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#define NS7520_ETH_HT1_HT1 (0x0000FFFF) /* CRC value 15-0 */
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/* HT2 Hash Table 2 Register Bit Fields*/
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#define NS7520_ETH_HT2_RES1 (0xFFFF0000) /* Reserved */
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#define NS7520_ETH_HT2_HT2 (0x0000FFFF) /* CRC value 31-16 */
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/* HT3 Hash Table 3 Register Bit Fields*/
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#define NS7520_ETH_HT3_RES1 (0xFFFF0000) /* Reserved */
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#define NS7520_ETH_HT3_HT3 (0x0000FFFF) /* CRC value 47-32 */
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/* HT4 Hash Table 4 Register Bit Fields*/
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#define NS7520_ETH_HT4_RES1 (0xFFFF0000) /* Reserved */
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#define NS7520_ETH_HT4_HT4 (0x0000FFFF) /* CRC value 63-48 */
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#endif /* CONFIG_DRIVER_NS7520_ETHERNET */
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#endif /* FS_NS7520_ETH_H */
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