upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
91 lines
1.9 KiB
91 lines
1.9 KiB
/*
|
|
* (C) Copyright 2000
|
|
* Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <mpc824x.h>
|
|
#include <pci.h>
|
|
#include <netdev.h>
|
|
|
|
int checkboard (void)
|
|
{
|
|
/*TODO: Check processor type */
|
|
|
|
puts ( "Board: Sandpoint "
|
|
#ifdef CONFIG_MPC8240
|
|
"8240"
|
|
#endif
|
|
#ifdef CONFIG_MPC8245
|
|
"8245"
|
|
#endif
|
|
" Unity ##Test not implemented yet##\n");
|
|
return 0;
|
|
}
|
|
|
|
#if 0 /* NOT USED */
|
|
int checkflash (void)
|
|
{
|
|
/* TODO: XXX XXX XXX */
|
|
printf ("## Test not implemented yet ##\n");
|
|
|
|
return (0);
|
|
}
|
|
#endif
|
|
|
|
phys_size_t initdram (int board_type)
|
|
{
|
|
long size;
|
|
long new_bank0_end;
|
|
long mear1;
|
|
long emear1;
|
|
|
|
size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
|
|
|
|
new_bank0_end = size - 1;
|
|
mear1 = mpc824x_mpc107_getreg(MEAR1);
|
|
emear1 = mpc824x_mpc107_getreg(EMEAR1);
|
|
mear1 = (mear1 & 0xFFFFFF00) |
|
|
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
|
|
emear1 = (emear1 & 0xFFFFFF00) |
|
|
((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
|
|
mpc824x_mpc107_setreg(MEAR1, mear1);
|
|
mpc824x_mpc107_setreg(EMEAR1, emear1);
|
|
|
|
return (size);
|
|
}
|
|
|
|
/*
|
|
* Initialize PCI Devices, report devices found.
|
|
*/
|
|
#ifndef CONFIG_PCI_PNP
|
|
static struct pci_config_table pci_sandpoint_config_table[] = {
|
|
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
|
|
pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
|
|
PCI_ENET0_MEMADDR,
|
|
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
|
|
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID,
|
|
pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
|
|
PCI_ENET1_MEMADDR,
|
|
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
|
|
{ }
|
|
};
|
|
#endif
|
|
|
|
struct pci_controller hose = {
|
|
#ifndef CONFIG_PCI_PNP
|
|
config_table: pci_sandpoint_config_table,
|
|
#endif
|
|
};
|
|
|
|
void pci_init_board(void)
|
|
{
|
|
pci_mpc824x_init(&hose);
|
|
}
|
|
|
|
int board_eth_init(bd_t *bis)
|
|
{
|
|
return pci_eth_init(bis);
|
|
}
|
|
|