upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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148 lines
3.9 KiB
148 lines
3.9 KiB
/*
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* NAND boot for Freescale Enhanced Local Bus Controller, Flash Control Machine
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*
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* (C) Copyright 2006-2008
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* Copyright (c) 2008 Freescale Semiconductor, Inc.
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* Author: Scott Wood <scottwood@freescale.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/immap_83xx.h>
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#include <asm/fsl_lbc.h>
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#include <linux/mtd/nand.h>
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#define WINDOW_SIZE 8192
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static void nand_wait(void)
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{
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lbus83xx_t *regs = (lbus83xx_t *)(CFG_IMMR + 0x5000);
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for (;;) {
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uint32_t status = in_be32(®s->ltesr);
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if (status == 1)
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return;
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if (status & 1) {
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puts("read failed (ltesr)\n");
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for (;;);
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}
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}
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}
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static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
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{
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lbus83xx_t *regs = (lbus83xx_t *)(CFG_IMMR + 0x5000);
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uchar *buf = (uchar *)CFG_NAND_BASE;
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int large = in_be32(®s->bank[0].or) & OR_FCM_PGS;
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int block_shift = large ? 17 : 14;
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int block_size = 1 << block_shift;
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int page_size = large ? 2048 : 512;
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int bad_marker = large ? page_size + 0 : page_size + 5;
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int fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT) | 2;
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int pos = 0;
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if (offs & (block_size - 1)) {
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puts("bad offset\n");
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for (;;);
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}
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if (large) {
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fmr |= FMR_ECCM;
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out_be32(®s->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
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(NAND_CMD_READSTART << FCR_CMD1_SHIFT));
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out_be32(®s->fir,
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(FIR_OP_CW0 << FIR_OP0_SHIFT) |
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(FIR_OP_CA << FIR_OP1_SHIFT) |
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(FIR_OP_PA << FIR_OP2_SHIFT) |
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(FIR_OP_CW1 << FIR_OP3_SHIFT) |
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(FIR_OP_RBW << FIR_OP4_SHIFT));
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} else {
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out_be32(®s->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
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out_be32(®s->fir,
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(FIR_OP_CW0 << FIR_OP0_SHIFT) |
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(FIR_OP_CA << FIR_OP1_SHIFT) |
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(FIR_OP_PA << FIR_OP2_SHIFT) |
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(FIR_OP_RBW << FIR_OP3_SHIFT));
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}
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out_be32(®s->fbcr, 0);
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clrsetbits_be32(®s->bank[0].br, BR_DECC, BR_DECC_CHK_GEN);
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while (pos < uboot_size) {
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int i = 0;
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out_be32(®s->fbar, offs >> block_shift);
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do {
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int j;
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unsigned int page_offs = (offs & (block_size - 1)) << 1;
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out_be32(®s->ltesr, ~0);
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out_be32(®s->lteatr, 0);
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out_be32(®s->fpar, page_offs);
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out_be32(®s->fmr, fmr);
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out_be32(®s->lsor, 0);
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nand_wait();
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page_offs %= WINDOW_SIZE;
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/*
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* If either of the first two pages are marked bad,
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* continue to the next block.
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*/
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if (i++ < 2 && buf[page_offs + bad_marker] != 0xff) {
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puts("skipping\n");
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offs = (offs + block_size) & ~(block_size - 1);
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pos &= ~(block_size - 1);
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break;
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}
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for (j = 0; j < page_size; j++)
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dst[pos + j] = buf[page_offs + j];
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pos += page_size;
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offs += page_size;
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} while (offs & (block_size - 1));
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}
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}
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/*
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* The main entry for NAND booting. It's necessary that SDRAM is already
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* configured and available since this code loads the main U-Boot image
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* from NAND into SDRAM and starts it from there.
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*/
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void nand_boot(void)
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{
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__attribute__((noreturn)) void (*uboot)(void);
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/*
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* Load U-Boot image from NAND into RAM
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*/
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nand_load(CFG_NAND_U_BOOT_OFFS, CFG_NAND_U_BOOT_SIZE,
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(uchar *)CFG_NAND_U_BOOT_DST);
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/*
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* Jump to U-Boot image
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*/
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puts("transfering control\n");
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uboot = (void *)CFG_NAND_U_BOOT_START;
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uboot();
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}
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