upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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279 lines
7.8 KiB
279 lines
7.8 KiB
/*
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* (C) Copyright 2015
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* Based on:
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* Copyright (C) 2012 Freescale Semiconductor, Inc.
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*
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* Author: Fabio Estevam <fabio.estevam@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-pins.h>
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#include <linux/errno.h>
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#include <asm/gpio.h>
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#include <asm/imx-common/iomux-v3.h>
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#include <asm/imx-common/boot_mode.h>
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#include <asm/imx-common/mxc_i2c.h>
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#include <asm/imx-common/video.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/arch/mxc_hdmi.h>
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#include <asm/arch/crm_regs.h>
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#include <linux/fb.h>
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#include <ipu_pixfmt.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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#include <pwm.h>
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struct i2c_pads_info i2c_pad_info3 = {
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.scl = {
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.i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
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.gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
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.gp = IMX_GPIO_NR(3, 17)
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},
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.sda = {
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.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
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.gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
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.gp = IMX_GPIO_NR(3, 18)
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}
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};
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iomux_v3_cfg_t const uart1_pads[] = {
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MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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iomux_v3_cfg_t const uart5_pads[] = {
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MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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iomux_v3_cfg_t const gpio_pads[] = {
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/* LED enable */
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MX6_PAD_SD4_DAT5__GPIO2_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* spi flash WP protect */
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MX6_PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* backlight enable */
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MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* LED yellow */
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MX6_PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* LED red */
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MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* LED green */
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MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* LED blue */
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MX6_PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* i2c4 scl */
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MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* i2c4 sda */
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MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* spi CS 1 */
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MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static iomux_v3_cfg_t const misc_pads[] = {
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MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* OTG Power enable */
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MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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iomux_v3_cfg_t const enet_pads[] = {
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MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(0x4001b0a8),
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MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
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};
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static void setup_iomux_enet(void)
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{
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struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
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imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
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/* set GPIO_16 as ENET_REF_CLK_OUT */
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setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
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}
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static iomux_v3_cfg_t const backlight_pads[] = {
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MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_SD4_DAT1__PWM3_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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iomux_v3_cfg_t const ecspi4_pads[] = {
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MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static iomux_v3_cfg_t const display_pads[] = {
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MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(DISP_PAD_CTRL),
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MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
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MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
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MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
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MX6_PAD_DI0_PIN4__GPIO4_IO20,
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MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
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MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
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MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
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MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
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MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
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MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
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MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
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MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
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MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
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MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
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MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
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MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
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MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
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MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
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MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
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MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
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MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
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MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
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MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
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MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
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MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
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MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
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MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
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MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
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};
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int board_spi_cs_gpio(unsigned bus, unsigned cs)
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{
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return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
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? (IMX_GPIO_NR(3, 20)) : -1;
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}
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static void setup_spi(void)
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{
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int i;
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imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads));
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for (i = 0; i < 3; i++)
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enable_spi_clk(true, i);
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/* set cs1 to high */
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gpio_direction_output(ECSPI4_CS1, 1);
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}
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static void setup_iomux_uart(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
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}
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int board_eth_init(bd_t *bis)
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{
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struct iomuxc *iomuxc_regs =
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(struct iomuxc *)IOMUXC_BASE_ADDR;
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int ret;
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/* clear gpr1[14], gpr1[18:17] to select anatop clock */
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clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
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ret = enable_fec_anatop_clock(0, ENET_50MHZ);
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if (ret)
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return ret;
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setup_iomux_enet();
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return cpu_eth_init(bis);
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}
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static void enable_lvds(struct display_info_t const *dev)
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{
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imx_iomux_v3_setup_multiple_pads(
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display_pads,
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ARRAY_SIZE(display_pads));
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imx_iomux_v3_setup_multiple_pads(
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backlight_pads,
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ARRAY_SIZE(backlight_pads));
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/* enable backlight PWM 3 */
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if (pwm_init(2, 0, 0))
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goto error;
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/* duty cycle 500ns, period: 3000ns */
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if (pwm_config(2, 500, 3000))
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goto error;
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if (pwm_enable(2))
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goto error;
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return;
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error:
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puts("error init pwm for backlight\n");
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return;
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}
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static void setup_display(void)
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{
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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int reg;
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enable_ipu_clock();
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reg = readl(&mxc_ccm->cs2cdr);
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/* select pll 5 clock */
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reg &= MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK;
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reg &= MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK;
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writel(reg, &mxc_ccm->cs2cdr);
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imx_iomux_v3_setup_multiple_pads(backlight_pads,
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ARRAY_SIZE(backlight_pads));
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}
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static void setup_iomux_gpio(void)
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{
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imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
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}
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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setup_iomux_gpio();
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setup_display();
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return 0;
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}
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static void setup_i2c4(void)
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{
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/* i2c4 not used, set it to gpio input */
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gpio_request(IMX_GPIO_NR(1, 7), "i2c4_scl");
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gpio_direction_input(IMX_GPIO_NR(1, 7));
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gpio_request(IMX_GPIO_NR(1, 8), "i2c4_sda");
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gpio_direction_input(IMX_GPIO_NR(1, 8));
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}
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static void setup_board_gpio(void)
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{
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/* enable LED */
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gpio_request(IMX_GPIO_NR(2, 13), "LED ena");
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gpio_direction_output(IMX_GPIO_NR(2, 13), 0);
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gpio_request(IMX_GPIO_NR(1, 3), "LED yellow");
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gpio_direction_output(IMX_GPIO_NR(1, 3), 1);
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gpio_request(IMX_GPIO_NR(1, 4), "LED red");
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gpio_direction_output(IMX_GPIO_NR(1, 4), 1);
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gpio_request(IMX_GPIO_NR(1, 5), "LED green");
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gpio_direction_output(IMX_GPIO_NR(1, 5), 1);
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gpio_request(IMX_GPIO_NR(1, 6), "LED blue");
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gpio_direction_output(IMX_GPIO_NR(1, 6), 1);
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}
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static void setup_board_spi(void)
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{
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}
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