upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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156 lines
3.8 KiB
156 lines
3.8 KiB
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
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*
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* Copyright (C) 2006 Micronas GmbH
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*/
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#ifndef _BCU_H
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#define _BCU_H
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enum bcu_tags {
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BCU_VBV1 = 0,
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BCU_VBV2 = 1,
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BCU_BSS1 = 2,
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BCU_BSS2 = 3,
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BCU_TSD_TXT = 4,
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BCU_TSD_SUBTITLES = 5,
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BCU_TSD_PES_0 = 6,
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BCU_TSD_PES_1 = 7,
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BCU_TSD_PES_2 = 8,
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BCU_TSD_PES_3 = 9,
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BCU_TSIO_RECORD_0 = 10,
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BCU_TSIO_RECORD_1 = 11,
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BCU_TSIO_PLAYBACK_0 = 12,
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BCU_TSIO_PLAYBACK_1 = 13,
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BCU_SECURE_BUFFER = 14,
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BCU_PCM1 = 15,
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BCU_PCM2 = 16,
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BCU_BSS_COPY = 17,
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BCU_BSS_EXT1 = 18,
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BCU_BSS_EXT2 = 19,
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BCU_PCM_JINGLE = 20,
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BCU_EBI_CPU_BUFFER = 21,
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BCU_PCM_DELAY = 22,
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BCU_FH_BUFFER_0 = 23,
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BCU_FH_BUFFER_1 = 24,
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BCU_TSD_SECTION_0 = 25,
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BCU_TSD_SECTION_1 = 26,
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BCU_TSD_SECTION_2 = 27,
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BCU_TSD_SECTION_3 = 28,
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BCU_TSD_SECTION_4 = 29,
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BCU_TSD_SECTION_5 = 30,
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BCU_TSD_SECTION_6 = 31,
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BCU_TSD_SECTION_7 = 32,
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BCU_TSD_SECTION_8 = 33,
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BCU_TSD_SECTION_9 = 34,
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BCU_TSD_SECTION_10 = 35,
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BCU_TSD_SECTION_11 = 36,
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BCU_TSD_SECTION_12 = 37,
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BCU_TSD_SECTION_13 = 38,
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BCU_TSD_SECTION_14 = 39,
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BCU_TSD_SECTION_15 = 40,
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BCU_TSD_SECTION_16 = 41,
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BCU_TSD_SECTION_17 = 42,
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BCU_TSD_SECTION_18 = 43,
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BCU_TSD_SECTION_19 = 44,
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BCU_TSD_SECTION_20 = 45,
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BCU_TSD_SECTION_21 = 46,
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BCU_TSD_SECTION_22 = 47,
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BCU_TSD_SECTION_23 = 48,
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BCU_TSD_SECTION_24 = 49,
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BCU_TSD_SECTION_25 = 50,
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BCU_TSD_SECTION_26 = 51,
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BCU_TSD_SECTION_27 = 52,
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BCU_TSD_SECTION_28 = 53,
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BCU_TSD_SECTION_29 = 54,
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BCU_TSD_SECTION_30 = 55,
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BCU_TSD_SECTION_31 = 56,
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BCU_TSD_SECTION_32 = 57,
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BCU_TSD_SECTION_33 = 58,
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BCU_TSD_SECTION_34 = 59,
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BCU_TSD_SECTION_35 = 60,
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BCU_TSD_SECTION_36 = 61,
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BCU_TSD_SECTION_37 = 62,
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BCU_TSD_SECTION_38 = 63,
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BCU_TSD_SECTION_39 = 64,
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BCU_TSD_SECTION_40 = 65,
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BCU_TSD_SECTION_41 = 66,
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BCU_TSD_SECTION_42 = 67,
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BCU_TSD_SECTION_43 = 68,
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BCU_TSD_SECTION_44 = 69,
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BCU_TSD_SECTION_45 = 70,
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BCU_TSD_SECTION_46 = 71,
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BCU_TSD_SECTION_47 = 72,
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BCU_TSD_SECTION_48 = 73,
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BCU_TSD_SECTION_49 = 74,
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BCU_TSD_SECTION_50 = 75,
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BCU_TSD_SECTION_51 = 76,
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BCU_TSD_SECTION_52 = 77,
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BCU_TSD_SECTION_53 = 78,
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BCU_TSIO_RECORD_2 = 79,
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BCU_TSIO_RECORD_3 = 80,
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BCU_TSIO_RECORD_4 = 81,
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BCU_TSIO_RECORD_5 = 82,
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BCU_TSIO_RECORD_6 = 83,
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BCU_TSIO_RECORD_7 = 84,
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BCU_TSIO_RECORD_8 = 85,
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BCU_TSIO_RECORD_9 = 86,
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BCU_PCM_DELAY_LINEAR = 87,
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BCU_VD_MASTER_USER_DATA = 88,
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BCU_VD_SLAVE_USER_DATA = 89,
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BCU_VD_MASTER_REF0 = 90,
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BCU_VD_MASTER_REF1 = 91,
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BCU_VD_SLAVE_REF0 = 92,
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BCU_VD_SLAVE_REF1 = 93,
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BCU_VD_MASTER_DISP0_Y = 94,
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BCU_VD_MASTER_DISP1_Y = 95,
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BCU_VD_MASTER_DISP2_Y = 96,
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BCU_VD_MASTER_DISP0_C = 97,
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BCU_VD_MASTER_DISP1_C = 98,
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BCU_VD_MASTER_DISP2_C = 99,
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BCU_VD_SLAVE_DISP0_Y = 100,
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BCU_VD_SLAVE_DISP1_Y = 101,
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BCU_VD_SLAVE_DISP2_Y = 102,
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BCU_VD_SLAVE_DISP0_C = 103,
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BCU_VD_SLAVE_DISP1_C = 104,
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BCU_VD_SLAVE_DISP2_C = 105,
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BCU_CLUT_BUFFER_0 = 106,
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BCU_CLUT_BUFFER_1 = 107,
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BCU_OSD_FRAME_BUFFER_0 = 108,
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BCU_OSD_FRAME_BUFFER_1 = 109,
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BCU_GRAPHIC_FRAME_BUFFER0 = 110,
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BCU_GRAPHIC_FRAME_BUFFER1 = 111,
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BCU_DVP_VBI_REINSERTION = 112,
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BCU_DVP_OSD_FRAME_BUFFER0 = 113,
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BCU_DVP_OSD_FRAME_BUFFER1 = 114,
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BCU_GAI_BUFFER = 115,
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BCU_GA_SRC_BUFFER_0 = 116,
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BCU_GA_SRC_BUFFER_1 = 117,
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BCU_USB_BUFFER_0 = 118,
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BCU_USB_BUFFER_1 = 119,
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BCU_FE_3DCOMB_0 = 120,
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BCU_FE_3DCOMB_1 = 121,
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BCU_FE_3DCOMB_2 = 122,
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BCU_FE_3DCOMB_3 = 123,
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BCU_TNR_BUFFER_0 = 124,
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BCU_TNR_BUFFER_1 = 125,
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BCU_TNR_BUFFER_2 = 126,
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BCU_MVAL_BUFFER = 127,
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BCU_RC_BUFFER_0 = 128,
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BCU_RC_BUFFER_1 = 129,
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BCU_RC_BUFFER_2 = 130,
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BCU_RC_BUFFER_3 = 131,
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BCU_PIP_BUFFER_0 = 132,
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BCU_PIP_BUFFER_1 = 133,
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BCU_PIP_BUFFER_2 = 134,
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BCU_PIP_BUFFER_3 = 135,
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BCU_EWARP_BUFFER = 136,
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BCU_OSD_BUFFER_0 = 137,
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BCU_OSD_BUFFER_1 = 138,
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BCU_GLOBAL_BUFFER_0 = 139,
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BCU_GLOBAL_BUFFER_1 = 140,
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BCU_MAX = 141
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};
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#endif /* _BCU_H */
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