upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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802 lines
23 KiB
802 lines
23 KiB
/*
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* (C) Copyright 2007-2009
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* Larry Johnson, lrj@acm.org
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*
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* (C) Copyright 2006-2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* (C) Copyright 2006
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* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
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* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <fdt_support.h>
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#include <i2c.h>
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#include <libfdt.h>
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#include <ppc440.h>
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#include <asm/bitops.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/ppc4xx-uic.h>
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#include <asm/processor.h>
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DECLARE_GLOBAL_DATA_PTR;
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extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
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ulong flash_get_size(ulong base, int banknum);
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#if defined(CONFIG_KORAT_PERMANENT)
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void korat_buzzer(int const on)
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{
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if (on) {
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out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05,
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in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05) | 0x80);
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} else {
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out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05,
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in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05) & ~0x80);
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}
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}
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#endif
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int board_early_init_f(void)
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{
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uint32_t sdr0_pfc1, sdr0_pfc2;
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uint32_t reg;
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int eth;
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#if defined(CONFIG_KORAT_PERMANENT)
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unsigned mscount;
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extern void korat_branch_absolute(uint32_t addr);
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for (mscount = 0; mscount < CONFIG_SYS_KORAT_MAN_RESET_MS; ++mscount) {
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udelay(1000);
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if (gpio_read_in_bit(CONFIG_SYS_GPIO_RESET_PRESSED_)) {
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/* This call does not return. */
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korat_branch_absolute(
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CONFIG_SYS_FLASH1_TOP - 2 * CONFIG_ENV_SECT_SIZE - 4);
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}
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}
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korat_buzzer(1);
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while (!gpio_read_in_bit(CONFIG_SYS_GPIO_RESET_PRESSED_))
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udelay(1000);
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korat_buzzer(0);
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#endif
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mtdcr(EBC0_CFGADDR, EBC0_CFG);
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mtdcr(EBC0_CFGDATA, 0xb8400000);
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/*
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* Setup the interrupt controller polarities, triggers, etc.
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*/
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mtdcr(UIC0SR, 0xffffffff); /* clear all */
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mtdcr(UIC0ER, 0x00000000); /* disable all */
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mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
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mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */
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mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
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mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
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mtdcr(UIC0SR, 0xffffffff); /* clear all */
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mtdcr(UIC1SR, 0xffffffff); /* clear all */
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mtdcr(UIC1ER, 0x00000000); /* disable all */
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mtdcr(UIC1CR, 0x00000000); /* all non-critical */
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mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
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mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
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mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
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mtdcr(UIC1SR, 0xffffffff); /* clear all */
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mtdcr(UIC2SR, 0xffffffff); /* clear all */
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mtdcr(UIC2ER, 0x00000000); /* disable all */
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mtdcr(UIC2CR, 0x00000000); /* all non-critical */
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mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
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mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
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mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
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mtdcr(UIC2SR, 0xffffffff); /* clear all */
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/*
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* Take sim card reader and CF controller out of reset. Also enable PHY
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* auto-detect until board-specific PHY resets are available.
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*/
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out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02, 0xC0);
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/* Configure the two Ethernet PHYs. For each PHY, configure for fiber
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* if the SFP module is present, and for copper if it is not present.
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*/
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for (eth = 0; eth < 2; ++eth) {
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if (gpio_read_in_bit(CONFIG_SYS_GPIO_SFP0_PRESENT_ + eth)) {
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/* SFP module not present: configure PHY for copper. */
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/* Set PHY to autonegotate 10 MB, 100MB, or 1 GB */
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out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03,
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in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03) |
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0x06 << (4 * eth));
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} else {
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/* SFP module present: configure PHY for fiber and
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enable output */
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gpio_write_bit(CONFIG_SYS_GPIO_PHY0_FIBER_SEL + eth, 1);
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gpio_write_bit(CONFIG_SYS_GPIO_SFP0_TX_EN_ + eth, 0);
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}
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}
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/* enable Ethernet: set GPIO45 and GPIO46 to 1 */
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gpio_write_bit(CONFIG_SYS_GPIO_PHY0_EN, 1);
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gpio_write_bit(CONFIG_SYS_GPIO_PHY1_EN, 1);
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/* Wait 1 ms, then enable Fiber signal detect to PHYs. */
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udelay(1000);
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out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03,
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in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03) | 0x88);
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/* select Ethernet (and optionally IIC1) pins */
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mfsdr(SDR0_PFC1, sdr0_pfc1);
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sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
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SDR0_PFC1_SELECT_CONFIG_4;
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#ifdef CONFIG_I2C_MULTI_BUS
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sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL);
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#endif
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mfsdr(SDR0_PFC2, sdr0_pfc2);
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sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
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SDR0_PFC2_SELECT_CONFIG_4;
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mtsdr(SDR0_PFC2, sdr0_pfc2);
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mtsdr(SDR0_PFC1, sdr0_pfc1);
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/* PCI arbiter enabled */
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mfsdr(SDR0_PCI0, reg);
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mtsdr(SDR0_PCI0, 0x80000000 | reg);
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return 0;
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}
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/*
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* The boot flash on CS0 normally has its write-enable pin disabled, and so will
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* not respond to CFI commands. This routine therefore fills in the flash
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* information for the boot flash. (The flash at CS1 operates normally.)
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*/
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ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
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{
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uint32_t addr;
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int i;
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if (1 != banknum)
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return 0;
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info->size = CONFIG_SYS_FLASH0_SIZE;
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info->sector_count = CONFIG_SYS_FLASH0_SIZE / 0x20000;
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info->flash_id = 0x01000000;
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info->portwidth = 2;
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info->chipwidth = 2;
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info->buffer_size = 32;
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info->erase_blk_tout = 16384;
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info->write_tout = 2;
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info->buffer_write_tout = 5;
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info->vendor = 2;
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info->cmd_reset = 0x00F0;
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info->interface = 2;
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info->legacy_unlock = 0;
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info->manufacturer_id = 1;
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info->device_id = 0x007E;
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#if CONFIG_SYS_FLASH0_SIZE == 0x01000000
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info->device_id2 = 0x2101;
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#elif CONFIG_SYS_FLASH0_SIZE == 0x04000000
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info->device_id2 = 0x2301;
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#else
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#error Unable to set device_id2 for current CONFIG_SYS_FLASH0_SIZE
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#endif
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info->ext_addr = 0x0040;
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info->cfi_version = 0x3133;
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info->cfi_offset = 0x0055;
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info->addr_unlock1 = 0x00000555;
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info->addr_unlock2 = 0x000002AA;
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info->name = "CFI conformant";
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for (i = 0, addr = -info->size;
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i < info->sector_count;
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++i, addr += 0x20000) {
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info->start[i] = addr;
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info->protect[i] = 0x00;
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}
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return 1;
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}
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static int man_data_read(unsigned int addr)
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{
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/*
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* Read an octet of data from address "addr" in the manufacturer's
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* information serial EEPROM, or -1 on error.
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*/
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u8 data[2];
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if (0 != i2c_probe(MAN_DATA_EEPROM_ADDR) ||
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0 != i2c_read(MAN_DATA_EEPROM_ADDR, addr, 1, data, 1)) {
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debug("man_data_read(0x%02X) failed\n", addr);
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return -1;
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}
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debug("man_info_read(0x%02X) returned 0x%02X\n", addr, data[0]);
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return data[0];
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}
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static unsigned int man_data_field_addr(unsigned int const field)
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{
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/*
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* The manufacturer's information serial EEPROM contains a sequence of
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* zero-delimited fields. Return the starting address of field "field",
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* or 0 on error.
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*/
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unsigned addr, i;
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if (0 == field || 'A' != man_data_read(0) || '\0' != man_data_read(1))
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/* Only format "A" is currently supported */
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return 0;
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for (addr = 2, i = 1; i < field && addr < 256; ++addr) {
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if ('\0' == man_data_read(addr))
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++i;
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}
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return (addr < 256) ? addr : 0;
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}
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static char *man_data_read_field(char s[], unsigned const field,
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unsigned const length)
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{
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/*
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* Place the null-terminated contents of field "field" of length
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* "length" from the manufacturer's information serial EEPROM into
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* string "s[length + 1]" and return a pointer to s, or return 0 on
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* error. In either case the original contents of s[] is not preserved.
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*/
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unsigned addr, i;
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addr = man_data_field_addr(field);
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if (0 == addr || addr + length >= 255)
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return 0;
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for (i = 0; i < length; ++i) {
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int const c = man_data_read(addr++);
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if (c <= 0)
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return 0;
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s[i] = (char)c;
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}
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if (0 != man_data_read(addr))
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return 0;
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s[i] = '\0';
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return s;
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}
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static void set_serial_number(void)
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{
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/*
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* If the environmental variable "serial#" is not set, try to set it
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* from the manufacturer's information serial EEPROM.
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*/
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char s[MAN_INFO_LENGTH + MAN_MAC_ADDR_LENGTH + 2];
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if (getenv("serial#"))
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return;
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if (!man_data_read_field(s, MAN_INFO_FIELD, MAN_INFO_LENGTH))
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return;
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s[MAN_INFO_LENGTH] = '-';
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if (!man_data_read_field(s + MAN_INFO_LENGTH + 1, MAN_MAC_ADDR_FIELD,
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MAN_MAC_ADDR_LENGTH))
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return;
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setenv("serial#", s);
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}
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static void set_mac_addresses(void)
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{
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/*
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* If the environmental variables "ethaddr" and/or "eth1addr" are not
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* set, try to set them from the manufacturer's information serial
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* EEPROM.
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*/
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#if MAN_MAC_ADDR_LENGTH % 2 != 0
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#error MAN_MAC_ADDR_LENGTH must be an even number
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#endif
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char s[(3 * MAN_MAC_ADDR_LENGTH) / 2];
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char *src;
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char *dst;
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if (0 != getenv("ethaddr") && 0 != getenv("eth1addr"))
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return;
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if (0 == man_data_read_field(s + (MAN_MAC_ADDR_LENGTH / 2) - 1,
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MAN_MAC_ADDR_FIELD, MAN_MAC_ADDR_LENGTH))
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return;
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for (src = s + (MAN_MAC_ADDR_LENGTH / 2) - 1, dst = s; src != dst;) {
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*dst++ = *src++;
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*dst++ = *src++;
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*dst++ = ':';
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}
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if (0 == getenv("ethaddr"))
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setenv("ethaddr", s);
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if (0 == getenv("eth1addr")) {
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++s[((3 * MAN_MAC_ADDR_LENGTH) / 2) - 2];
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setenv("eth1addr", s);
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}
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}
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int misc_init_r(void)
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{
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uint32_t pbcr;
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int size_val;
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uint32_t reg;
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unsigned long usb2d0cr = 0;
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unsigned long usb2phy0cr, usb2h0cr = 0;
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unsigned long sdr0_pfc1;
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uint32_t const flash1_size = gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE;
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char const *const act = getenv("usbact");
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char const *const usbcf = getenv("korat_usbcf");
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/*
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* Re-do FLASH1 sizing and adjust flash start and offset.
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*/
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gd->bd->bi_flashstart = CONFIG_SYS_FLASH1_TOP - flash1_size;
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gd->bd->bi_flashoffset = 0;
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mtdcr(EBC0_CFGADDR, PB1CR);
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pbcr = mfdcr(EBC0_CFGDATA);
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size_val = ffs(flash1_size) - 21;
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pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
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mtdcr(EBC0_CFGADDR, PB1CR);
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mtdcr(EBC0_CFGDATA, pbcr);
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/*
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* Re-check to get correct base address
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*/
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flash_get_size(gd->bd->bi_flashstart, 0);
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/*
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* Re-do FLASH1 sizing and adjust flash offset to reserve space for
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* environment
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*/
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gd->bd->bi_flashoffset =
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CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - CONFIG_SYS_FLASH1_ADDR;
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mtdcr(EBC0_CFGADDR, PB1CR);
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pbcr = mfdcr(EBC0_CFGDATA);
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size_val = ffs(gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE) - 21;
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pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
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mtdcr(EBC0_CFGADDR, PB1CR);
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mtdcr(EBC0_CFGDATA, pbcr);
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/* Monitor protection ON by default */
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#if defined(CONFIG_KORAT_PERMANENT)
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(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
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CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
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flash_info + 1);
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#else
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(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
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CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
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flash_info);
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#endif
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/* Env protection ON by default */
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(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
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CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
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flash_info);
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(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
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CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
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flash_info);
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/*
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* USB suff...
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*/
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/*
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* Select the USB controller on the 440EPx ("ppc") or on the PCI bus
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* ("pci") for the CompactFlash.
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*/
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if (usbcf != NULL && (strcmp(usbcf, "ppc") == 0)) {
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/*
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* If environment variable "usbcf" is defined and set to "ppc",
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* then connect the CompactFlash controller to the PowerPC USB
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* port.
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*/
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printf("Attaching CompactFalsh controller to PPC USB\n");
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out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02,
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in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02) | 0x10);
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} else {
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if (usbcf != NULL && (strcmp(usbcf, "pci") != 0))
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printf("Warning: \"korat_usbcf\" is not set to a legal "
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"value (\"ppc\" or \"pci\")\n");
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printf("Attaching CompactFalsh controller to PCI USB\n");
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}
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if (act == NULL || strcmp(act, "hostdev") == 0) {
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/* SDR Setting */
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mfsdr(SDR0_PFC1, sdr0_pfc1);
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mfsdr(SDR0_USB2D0CR, usb2d0cr);
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mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
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mfsdr(SDR0_USB2H0CR, usb2h0cr);
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
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|
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
|
|
|
|
/*
|
|
* An 8-bit/60MHz interface is the only possible alternative
|
|
* when connecting the Device to the PHY
|
|
*/
|
|
usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
|
|
usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
|
|
|
|
/*
|
|
* To enable the USB 2.0 Device function
|
|
* through the UTMI interface
|
|
*/
|
|
usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
|
|
usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;
|
|
|
|
sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
|
|
sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;
|
|
|
|
mtsdr(SDR0_PFC1, sdr0_pfc1);
|
|
mtsdr(SDR0_USB2D0CR, usb2d0cr);
|
|
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
|
|
mtsdr(SDR0_USB2H0CR, usb2h0cr);
|
|
|
|
/* clear resets */
|
|
udelay(1000);
|
|
mtsdr(SDR0_SRST1, 0x00000000);
|
|
udelay(1000);
|
|
mtsdr(SDR0_SRST0, 0x00000000);
|
|
|
|
printf("USB: Host(int phy) Device(ext phy)\n");
|
|
|
|
} else if (strcmp(act, "dev") == 0) {
|
|
/*-------------------PATCH-------------------------------*/
|
|
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
|
|
|
|
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
|
|
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
|
|
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
|
|
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
|
|
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
|
|
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
|
|
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
|
|
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
|
|
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
|
|
|
|
udelay(1000);
|
|
mtsdr(SDR0_SRST1, 0x672c6000);
|
|
|
|
udelay(1000);
|
|
mtsdr(SDR0_SRST0, 0x00000080);
|
|
|
|
udelay(1000);
|
|
mtsdr(SDR0_SRST1, 0x60206000);
|
|
|
|
*(unsigned int *)(0xe0000350) = 0x00000001;
|
|
|
|
udelay(1000);
|
|
mtsdr(SDR0_SRST1, 0x60306000);
|
|
/*-------------------PATCH-------------------------------*/
|
|
|
|
/* SDR Setting */
|
|
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
|
|
mfsdr(SDR0_USB2H0CR, usb2h0cr);
|
|
mfsdr(SDR0_USB2D0CR, usb2d0cr);
|
|
mfsdr(SDR0_PFC1, sdr0_pfc1);
|
|
|
|
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
|
|
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
|
|
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
|
|
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
|
|
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
|
|
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
|
|
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
|
|
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
|
|
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
|
|
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
|
|
|
|
usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
|
|
usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
|
|
|
|
usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
|
|
usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;
|
|
|
|
sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
|
|
sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
|
|
|
|
mtsdr(SDR0_USB2H0CR, usb2h0cr);
|
|
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
|
|
mtsdr(SDR0_USB2D0CR, usb2d0cr);
|
|
mtsdr(SDR0_PFC1, sdr0_pfc1);
|
|
|
|
/* clear resets */
|
|
udelay(1000);
|
|
mtsdr(SDR0_SRST1, 0x00000000);
|
|
udelay(1000);
|
|
mtsdr(SDR0_SRST0, 0x00000000);
|
|
|
|
printf("USB: Device(int phy)\n");
|
|
}
|
|
|
|
mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */
|
|
reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
|
|
mtsdr(SDR0_SRST1, reg);
|
|
|
|
/*
|
|
* Clear PLB4A0_ACR[WRP]
|
|
* This fix will make the MAL burst disabling patch for the Linux
|
|
* EMAC driver obsolete.
|
|
*/
|
|
reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP;
|
|
mtdcr(PLB4_ACR, reg);
|
|
|
|
set_serial_number();
|
|
set_mac_addresses();
|
|
gpio_write_bit(CONFIG_SYS_GPIO_ATMEGA_RESET_, 1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int checkboard(void)
|
|
{
|
|
char const *const s = getenv("serial#");
|
|
u8 const rev = in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0);
|
|
|
|
printf("Board: Korat, Rev. %X", rev);
|
|
if (s)
|
|
printf(", serial# %s", s);
|
|
|
|
printf(".\n Ethernet PHY 0: ");
|
|
if (gpio_read_out_bit(CONFIG_SYS_GPIO_PHY0_FIBER_SEL))
|
|
printf("fiber");
|
|
else
|
|
printf("copper");
|
|
|
|
printf(", PHY 1: ");
|
|
if (gpio_read_out_bit(CONFIG_SYS_GPIO_PHY1_FIBER_SEL))
|
|
printf("fiber");
|
|
else
|
|
printf("copper");
|
|
|
|
printf(".\n");
|
|
#if defined(CONFIG_KORAT_PERMANENT)
|
|
printf(" Executing permanent copy of U-Boot.\n");
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
|
|
/*
|
|
* Assign interrupts to PCI devices.
|
|
*/
|
|
void korat_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
|
|
{
|
|
pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2);
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* pci_pre_init
|
|
*
|
|
* This routine is called just prior to registering the hose and gives
|
|
* the board the opportunity to check things. Returning a value of zero
|
|
* indicates that things are bad & PCI initialization should be aborted.
|
|
*
|
|
* Different boards may wish to customize the pci controller structure
|
|
* (add regions, override default access routines, etc) or perform
|
|
* certain pre-initialization actions.
|
|
*/
|
|
#if defined(CONFIG_PCI)
|
|
int pci_pre_init(struct pci_controller *hose)
|
|
{
|
|
unsigned long addr;
|
|
|
|
/*
|
|
* Set priority for all PLB3 devices to 0.
|
|
* Set PLB3 arbiter to fair mode.
|
|
*/
|
|
mfsdr(SD0_AMP1, addr);
|
|
mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
|
|
addr = mfdcr(PLB3_ACR);
|
|
mtdcr(PLB3_ACR, addr | 0x80000000);
|
|
|
|
/*
|
|
* Set priority for all PLB4 devices to 0.
|
|
*/
|
|
mfsdr(SD0_AMP0, addr);
|
|
mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
|
|
addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
|
|
mtdcr(PLB4_ACR, addr);
|
|
|
|
/*
|
|
* Set Nebula PLB4 arbiter to fair mode.
|
|
*/
|
|
/* Segment0 */
|
|
addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
|
|
addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
|
|
addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
|
|
addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
|
|
mtdcr(PLB0_ACR, addr);
|
|
|
|
/* Segment1 */
|
|
addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
|
|
addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
|
|
addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
|
|
addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
|
|
mtdcr(PLB1_ACR, addr);
|
|
|
|
#if defined(CONFIG_PCI_PNP)
|
|
hose->fixup_irq = korat_pci_fixup_irq;
|
|
#endif
|
|
|
|
return 1;
|
|
}
|
|
#endif /* defined(CONFIG_PCI) */
|
|
|
|
/*
|
|
* pci_target_init
|
|
*
|
|
* The bootstrap configuration provides default settings for the pci
|
|
* inbound map (PIM). But the bootstrap config choices are limited and
|
|
* may not be sufficient for a given board.
|
|
*/
|
|
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
|
|
void pci_target_init(struct pci_controller *hose)
|
|
{
|
|
/*
|
|
* Set up Direct MMIO registers
|
|
*/
|
|
/*
|
|
* PowerPC440EPX PCI Master configuration.
|
|
* Map one 1Gig range of PLB/processor addresses to PCI memory space.
|
|
* PLB address 0x80000000-0xBFFFFFFF
|
|
* ==> PCI address 0x80000000-0xBFFFFFFF
|
|
* Use byte reversed out routines to handle endianess.
|
|
* Make this region non-prefetchable.
|
|
*/
|
|
out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
|
|
/* - disabled b4 setting */
|
|
out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
|
|
out32r(PCIL0_PMM0PCILA,
|
|
CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
|
|
out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
|
|
out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
|
|
/* and enable region */
|
|
|
|
out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
|
|
/* - disabled b4 setting */
|
|
out32r(PCIL0_PMM1LA,
|
|
CONFIG_SYS_PCI_MEMBASE + 0x20000000); /* PMM0 Local Address */
|
|
out32r(PCIL0_PMM1PCILA,
|
|
CONFIG_SYS_PCI_MEMBASE + 0x20000000); /* PMM0 PCI Low Address */
|
|
out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
|
|
out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
|
|
/* and enable region */
|
|
|
|
out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
|
|
out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */
|
|
out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
|
|
out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */
|
|
|
|
/*
|
|
* Set up Configuration registers
|
|
*/
|
|
|
|
/* Program the board's subsystem id/vendor id */
|
|
pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
|
|
CONFIG_SYS_PCI_SUBSYS_VENDORID);
|
|
pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
|
|
|
|
/* Configure command register as bus master */
|
|
pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
|
|
|
|
/* 240nS PCI clock */
|
|
pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
|
|
|
|
/* No error reporting */
|
|
pci_write_config_word(0, PCI_ERREN, 0);
|
|
|
|
pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
|
|
|
|
/*
|
|
* Set up Configuration registers for on-board NEC uPD720101 USB
|
|
* controller.
|
|
*/
|
|
pci_write_config_dword(PCI_BDF(0x0, 0xC, 0x0), 0xE4, 0x00000020);
|
|
}
|
|
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
|
|
|
|
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
|
|
void pci_master_init(struct pci_controller *hose)
|
|
{
|
|
unsigned short temp_short;
|
|
|
|
/*
|
|
* Write the PowerPC440 EP PCI Configuration regs.
|
|
* Enable PowerPC440 EP to be a master on the PCI bus (PMM).
|
|
* Enable PowerPC440 EP to act as a PCI memory target (PTM).
|
|
*/
|
|
pci_read_config_word(0, PCI_COMMAND, &temp_short);
|
|
pci_write_config_word(0, PCI_COMMAND,
|
|
temp_short | PCI_COMMAND_MASTER |
|
|
PCI_COMMAND_MEMORY);
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* is_pci_host
|
|
*
|
|
* This routine is called to determine if a pci scan should be
|
|
* performed. With various hardware environments (especially cPCI and
|
|
* PPMC) it's insufficient to depend on the state of the arbiter enable
|
|
* bit in the strap register, or generic host/adapter assumptions.
|
|
*
|
|
* Rather than hard-code a bad assumption in the general 440 code, the
|
|
* 440 pci code requires the board to decide at runtime.
|
|
*
|
|
* Return 0 for adapter mode, non-zero for host (monarch) mode.
|
|
*/
|
|
#if defined(CONFIG_PCI)
|
|
int is_pci_host(struct pci_controller *hose)
|
|
{
|
|
/* Korat is always configured as host. */
|
|
return (1);
|
|
}
|
|
#endif /* defined(CONFIG_PCI) */
|
|
|
|
#if defined(CONFIG_POST)
|
|
/*
|
|
* Returns 1 if keys pressed to start the power-on long-running tests
|
|
* Called from board_init_f().
|
|
*/
|
|
int post_hotkeys_pressed(void)
|
|
{
|
|
return 0; /* No hotkeys supported */
|
|
}
|
|
#endif /* CONFIG_POST */
|
|
|
|
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
|
|
void ft_board_setup(void *blob, bd_t *bd)
|
|
{
|
|
u32 val[4];
|
|
int rc;
|
|
|
|
ft_cpu_setup(blob, bd);
|
|
|
|
/* Fixup NOR mapping */
|
|
val[0] = 1; /* chip select number */
|
|
val[1] = 0; /* always 0 */
|
|
val[2] = gd->bd->bi_flashstart;
|
|
val[3] = gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE;
|
|
rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
|
|
val, sizeof(val), 1);
|
|
if (rc)
|
|
printf("Unable to update property NOR mapping, err=%s\n",
|
|
fdt_strerror(rc));
|
|
}
|
|
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
|
|
|