upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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451 lines
12 KiB
451 lines
12 KiB
// SPDX-License-Identifier: GPL-2.0
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/**
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* dwc3-omap.c - OMAP Specific Glue layer
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*
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* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
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*
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* Authors: Felipe Balbi <balbi@ti.com>,
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* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
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*
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* Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/dwc3-omap.c) and ported
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* to uboot.
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*
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* commit 7ee2566ff5 : usb: dwc3: dwc3-omap: get rid of ->prepare()/->complete()
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*/
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#include <common.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <dm.h>
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#include <dwc3-omap-uboot.h>
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#include <linux/usb/dwc3-omap.h>
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#include <linux/ioport.h>
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#include <linux/usb/otg.h>
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#include <linux/compat.h>
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#include "linux-compat.h"
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/*
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* All these registers belong to OMAP's Wrapper around the
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* DesignWare USB3 Core.
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*/
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#define USBOTGSS_REVISION 0x0000
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#define USBOTGSS_SYSCONFIG 0x0010
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#define USBOTGSS_IRQ_EOI 0x0020
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#define USBOTGSS_EOI_OFFSET 0x0008
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#define USBOTGSS_IRQSTATUS_RAW_0 0x0024
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#define USBOTGSS_IRQSTATUS_0 0x0028
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#define USBOTGSS_IRQENABLE_SET_0 0x002c
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#define USBOTGSS_IRQENABLE_CLR_0 0x0030
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#define USBOTGSS_IRQ0_OFFSET 0x0004
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#define USBOTGSS_IRQSTATUS_RAW_1 0x0030
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#define USBOTGSS_IRQSTATUS_1 0x0034
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#define USBOTGSS_IRQENABLE_SET_1 0x0038
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#define USBOTGSS_IRQENABLE_CLR_1 0x003c
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#define USBOTGSS_IRQSTATUS_RAW_2 0x0040
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#define USBOTGSS_IRQSTATUS_2 0x0044
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#define USBOTGSS_IRQENABLE_SET_2 0x0048
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#define USBOTGSS_IRQENABLE_CLR_2 0x004c
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#define USBOTGSS_IRQSTATUS_RAW_3 0x0050
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#define USBOTGSS_IRQSTATUS_3 0x0054
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#define USBOTGSS_IRQENABLE_SET_3 0x0058
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#define USBOTGSS_IRQENABLE_CLR_3 0x005c
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#define USBOTGSS_IRQSTATUS_EOI_MISC 0x0030
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#define USBOTGSS_IRQSTATUS_RAW_MISC 0x0034
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#define USBOTGSS_IRQSTATUS_MISC 0x0038
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#define USBOTGSS_IRQENABLE_SET_MISC 0x003c
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#define USBOTGSS_IRQENABLE_CLR_MISC 0x0040
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#define USBOTGSS_IRQMISC_OFFSET 0x03fc
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#define USBOTGSS_UTMI_OTG_CTRL 0x0080
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#define USBOTGSS_UTMI_OTG_STATUS 0x0084
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#define USBOTGSS_UTMI_OTG_OFFSET 0x0480
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#define USBOTGSS_TXFIFO_DEPTH 0x0508
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#define USBOTGSS_RXFIFO_DEPTH 0x050c
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#define USBOTGSS_MMRAM_OFFSET 0x0100
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#define USBOTGSS_FLADJ 0x0104
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#define USBOTGSS_DEBUG_CFG 0x0108
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#define USBOTGSS_DEBUG_DATA 0x010c
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#define USBOTGSS_DEV_EBC_EN 0x0110
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#define USBOTGSS_DEBUG_OFFSET 0x0600
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/* SYSCONFIG REGISTER */
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#define USBOTGSS_SYSCONFIG_DMADISABLE (1 << 16)
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/* IRQ_EOI REGISTER */
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#define USBOTGSS_IRQ_EOI_LINE_NUMBER (1 << 0)
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/* IRQS0 BITS */
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#define USBOTGSS_IRQO_COREIRQ_ST (1 << 0)
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/* IRQMISC BITS */
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#define USBOTGSS_IRQMISC_DMADISABLECLR (1 << 17)
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#define USBOTGSS_IRQMISC_OEVT (1 << 16)
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#define USBOTGSS_IRQMISC_DRVVBUS_RISE (1 << 13)
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#define USBOTGSS_IRQMISC_CHRGVBUS_RISE (1 << 12)
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#define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE (1 << 11)
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#define USBOTGSS_IRQMISC_IDPULLUP_RISE (1 << 8)
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#define USBOTGSS_IRQMISC_DRVVBUS_FALL (1 << 5)
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#define USBOTGSS_IRQMISC_CHRGVBUS_FALL (1 << 4)
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#define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL (1 << 3)
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#define USBOTGSS_IRQMISC_IDPULLUP_FALL (1 << 0)
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#define USBOTGSS_INTERRUPTS (USBOTGSS_IRQMISC_OEVT | \
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USBOTGSS_IRQMISC_DRVVBUS_RISE | \
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USBOTGSS_IRQMISC_CHRGVBUS_RISE | \
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USBOTGSS_IRQMISC_DISCHRGVBUS_RISE | \
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USBOTGSS_IRQMISC_IDPULLUP_RISE | \
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USBOTGSS_IRQMISC_DRVVBUS_FALL | \
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USBOTGSS_IRQMISC_CHRGVBUS_FALL | \
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USBOTGSS_IRQMISC_DISCHRGVBUS_FALL | \
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USBOTGSS_IRQMISC_IDPULLUP_FALL)
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/* UTMI_OTG_CTRL REGISTER */
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#define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS (1 << 5)
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#define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS (1 << 4)
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#define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS (1 << 3)
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#define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP (1 << 0)
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/* UTMI_OTG_STATUS REGISTER */
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#define USBOTGSS_UTMI_OTG_STATUS_SW_MODE (1 << 31)
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#define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT (1 << 9)
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#define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8)
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#define USBOTGSS_UTMI_OTG_STATUS_IDDIG (1 << 4)
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#define USBOTGSS_UTMI_OTG_STATUS_SESSEND (1 << 3)
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#define USBOTGSS_UTMI_OTG_STATUS_SESSVALID (1 << 2)
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#define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID (1 << 1)
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struct dwc3_omap {
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struct device *dev;
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void __iomem *base;
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u32 utmi_otg_status;
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u32 utmi_otg_offset;
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u32 irqmisc_offset;
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u32 irq_eoi_offset;
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u32 debug_offset;
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u32 irq0_offset;
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u32 dma_status:1;
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struct list_head list;
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u32 index;
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};
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static LIST_HEAD(dwc3_omap_list);
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static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset)
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{
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return readl(base + offset);
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}
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static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value)
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{
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writel(value, base + offset);
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}
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static u32 dwc3_omap_read_utmi_status(struct dwc3_omap *omap)
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{
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return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS +
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omap->utmi_otg_offset);
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}
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static void dwc3_omap_write_utmi_status(struct dwc3_omap *omap, u32 value)
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{
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dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS +
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omap->utmi_otg_offset, value);
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}
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static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap)
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{
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return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0 -
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omap->irq0_offset);
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}
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static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value)
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{
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dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 -
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omap->irq0_offset, value);
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}
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static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap)
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{
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return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_MISC +
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omap->irqmisc_offset);
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}
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static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value)
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{
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dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC +
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omap->irqmisc_offset, value);
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}
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static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value)
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{
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dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC +
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omap->irqmisc_offset, value);
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}
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static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value)
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{
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dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 -
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omap->irq0_offset, value);
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}
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static void dwc3_omap_write_irqmisc_clr(struct dwc3_omap *omap, u32 value)
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{
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dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_MISC +
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omap->irqmisc_offset, value);
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}
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static void dwc3_omap_write_irq0_clr(struct dwc3_omap *omap, u32 value)
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{
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dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_0 -
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omap->irq0_offset, value);
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}
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static void dwc3_omap_set_mailbox(struct dwc3_omap *omap,
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enum omap_dwc3_vbus_id_status status)
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{
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u32 val;
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switch (status) {
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case OMAP_DWC3_ID_GROUND:
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dev_dbg(omap->dev, "ID GND\n");
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val = dwc3_omap_read_utmi_status(omap);
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val &= ~(USBOTGSS_UTMI_OTG_STATUS_IDDIG
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| USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
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| USBOTGSS_UTMI_OTG_STATUS_SESSEND);
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val |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID
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| USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
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dwc3_omap_write_utmi_status(omap, val);
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break;
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case OMAP_DWC3_VBUS_VALID:
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dev_dbg(omap->dev, "VBUS Connect\n");
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val = dwc3_omap_read_utmi_status(omap);
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val &= ~USBOTGSS_UTMI_OTG_STATUS_SESSEND;
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val |= USBOTGSS_UTMI_OTG_STATUS_IDDIG
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| USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
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| USBOTGSS_UTMI_OTG_STATUS_SESSVALID
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| USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
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dwc3_omap_write_utmi_status(omap, val);
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break;
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case OMAP_DWC3_ID_FLOAT:
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case OMAP_DWC3_VBUS_OFF:
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dev_dbg(omap->dev, "VBUS Disconnect\n");
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val = dwc3_omap_read_utmi_status(omap);
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val &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSVALID
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| USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
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| USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT);
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val |= USBOTGSS_UTMI_OTG_STATUS_SESSEND
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| USBOTGSS_UTMI_OTG_STATUS_IDDIG;
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dwc3_omap_write_utmi_status(omap, val);
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break;
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default:
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dev_dbg(omap->dev, "invalid state\n");
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}
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}
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static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
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{
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struct dwc3_omap *omap = _omap;
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u32 reg;
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reg = dwc3_omap_read_irqmisc_status(omap);
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if (reg & USBOTGSS_IRQMISC_DMADISABLECLR) {
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dev_dbg(omap->dev, "DMA Disable was Cleared\n");
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omap->dma_status = false;
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}
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if (reg & USBOTGSS_IRQMISC_OEVT)
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dev_dbg(omap->dev, "OTG Event\n");
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if (reg & USBOTGSS_IRQMISC_DRVVBUS_RISE)
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dev_dbg(omap->dev, "DRVVBUS Rise\n");
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if (reg & USBOTGSS_IRQMISC_CHRGVBUS_RISE)
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dev_dbg(omap->dev, "CHRGVBUS Rise\n");
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if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_RISE)
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dev_dbg(omap->dev, "DISCHRGVBUS Rise\n");
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if (reg & USBOTGSS_IRQMISC_IDPULLUP_RISE)
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dev_dbg(omap->dev, "IDPULLUP Rise\n");
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if (reg & USBOTGSS_IRQMISC_DRVVBUS_FALL)
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dev_dbg(omap->dev, "DRVVBUS Fall\n");
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if (reg & USBOTGSS_IRQMISC_CHRGVBUS_FALL)
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dev_dbg(omap->dev, "CHRGVBUS Fall\n");
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if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_FALL)
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dev_dbg(omap->dev, "DISCHRGVBUS Fall\n");
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if (reg & USBOTGSS_IRQMISC_IDPULLUP_FALL)
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dev_dbg(omap->dev, "IDPULLUP Fall\n");
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dwc3_omap_write_irqmisc_status(omap, reg);
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reg = dwc3_omap_read_irq0_status(omap);
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dwc3_omap_write_irq0_status(omap, reg);
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return IRQ_HANDLED;
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}
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static void dwc3_omap_enable_irqs(struct dwc3_omap *omap)
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{
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/* enable all IRQs */
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dwc3_omap_write_irq0_set(omap, USBOTGSS_IRQO_COREIRQ_ST);
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dwc3_omap_write_irqmisc_set(omap, USBOTGSS_INTERRUPTS);
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}
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static void dwc3_omap_disable_irqs(struct dwc3_omap *omap)
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{
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/* disable all IRQs */
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dwc3_omap_write_irq0_clr(omap, USBOTGSS_IRQO_COREIRQ_ST);
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dwc3_omap_write_irqmisc_clr(omap, USBOTGSS_INTERRUPTS);
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}
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static void dwc3_omap_map_offset(struct dwc3_omap *omap)
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{
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/*
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* Differentiate between OMAP5 and AM437x.
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*
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* For OMAP5(ES2.0) and AM437x wrapper revision is same, even
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* though there are changes in wrapper register offsets.
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*
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* Using dt compatible to differentiate AM437x.
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*/
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#ifdef CONFIG_AM43XX
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omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET;
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omap->irq0_offset = USBOTGSS_IRQ0_OFFSET;
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omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET;
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omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET;
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omap->debug_offset = USBOTGSS_DEBUG_OFFSET;
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#endif
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}
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static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap, int utmi_mode)
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{
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u32 reg;
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reg = dwc3_omap_read_utmi_status(omap);
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switch (utmi_mode) {
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case DWC3_OMAP_UTMI_MODE_SW:
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reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
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break;
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case DWC3_OMAP_UTMI_MODE_HW:
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reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
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break;
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default:
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dev_dbg(omap->dev, "UNKNOWN utmi mode %d\n", utmi_mode);
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}
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dwc3_omap_write_utmi_status(omap, reg);
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}
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/**
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* dwc3_omap_uboot_init - dwc3 omap uboot initialization code
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* @dev: struct dwc3_omap_device containing initialization data
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*
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* Entry point for dwc3 omap driver (equivalent to dwc3_omap_probe in linux
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* kernel driver). Pointer to dwc3_omap_device should be passed containing
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* base address and other initialization data. Returns '0' on success and
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* a negative value on failure.
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*
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* Generally called from board_usb_init() implemented in board file.
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*/
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int dwc3_omap_uboot_init(struct dwc3_omap_device *omap_dev)
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{
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u32 reg;
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struct device *dev = NULL;
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struct dwc3_omap *omap;
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omap = devm_kzalloc((struct udevice *)dev, sizeof(*omap), GFP_KERNEL);
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if (!omap)
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return -ENOMEM;
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omap->base = omap_dev->base;
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omap->index = omap_dev->index;
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dwc3_omap_map_offset(omap);
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dwc3_omap_set_utmi_mode(omap, omap_dev->utmi_mode);
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/* check the DMA Status */
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reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG);
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omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE);
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dwc3_omap_set_mailbox(omap, omap_dev->vbus_id_status);
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dwc3_omap_enable_irqs(omap);
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list_add_tail(&omap->list, &dwc3_omap_list);
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return 0;
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}
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/**
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* dwc3_omap_uboot_exit - dwc3 omap uboot cleanup code
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* @index: index of this controller
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*
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* Performs cleanup of memory allocated in dwc3_omap_uboot_init
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* (equivalent to dwc3_omap_remove in linux). index of _this_ controller
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* should be passed and should match with the index passed in
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* dwc3_omap_device during init.
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*
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* Generally called from board file.
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*/
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void dwc3_omap_uboot_exit(int index)
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{
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struct dwc3_omap *omap = NULL;
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list_for_each_entry(omap, &dwc3_omap_list, list) {
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if (omap->index != index)
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continue;
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dwc3_omap_disable_irqs(omap);
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list_del(&omap->list);
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kfree(omap);
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break;
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}
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}
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/**
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* dwc3_omap_uboot_interrupt_status - check the status of interrupt
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* @index: index of this controller
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*
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* Checks the status of interrupts and returns true if an interrupt
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* is detected or false otherwise.
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*
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* Generally called from board file.
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*/
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int dwc3_omap_uboot_interrupt_status(int index)
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{
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struct dwc3_omap *omap = NULL;
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list_for_each_entry(omap, &dwc3_omap_list, list)
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if (omap->index == index)
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return dwc3_omap_interrupt(-1, omap);
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return 0;
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}
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MODULE_ALIAS("platform:omap-dwc3");
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MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");
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