upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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156 lines
4.2 KiB
156 lines
4.2 KiB
/*
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* Memory sub-system initialization code for INCA-IP development board.
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*
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* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/regdef.h>
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#define EBU_MODUL_BASE 0xB8000200
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#define EBU_CLC(value) 0x0000(value)
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#define EBU_CON(value) 0x0010(value)
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#define EBU_ADDSEL0(value) 0x0020(value)
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#define EBU_ADDSEL1(value) 0x0024(value)
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#define EBU_ADDSEL2(value) 0x0028(value)
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#define EBU_BUSCON0(value) 0x0060(value)
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#define EBU_BUSCON1(value) 0x0064(value)
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#define EBU_BUSCON2(value) 0x0068(value)
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#define MC_MODUL_BASE 0xBF800000
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#define MC_ERRCAUSE(value) 0x0100(value)
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#define MC_ERRADDR(value) 0x0108(value)
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#define MC_IOGP(value) 0x0800(value)
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#define MC_SELFRFSH(value) 0x0A00(value)
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#define MC_CTRLENA(value) 0x1000(value)
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#define MC_MRSCODE(value) 0x1008(value)
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#define MC_CFGDW(value) 0x1010(value)
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#define MC_CFGPB0(value) 0x1018(value)
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#define MC_LATENCY(value) 0x1038(value)
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#define MC_TREFRESH(value) 0x1040(value)
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#define CGU_MODUL_BASE 0xBF107000
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#define CGU_PLL1CR(value) 0x0008(value)
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#define CGU_DIVCR(value) 0x0010(value)
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#define CGU_MUXCR(value) 0x0014(value)
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#define CGU_PLL1SR(value) 0x000C(value)
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.globl memsetup
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memsetup:
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/* EBU Initialization for the Flash CS0 and CS2.
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*/
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li t0, EBU_MODUL_BASE
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li t1, 0xA0000041
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sw t1, EBU_ADDSEL0(t0)
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#if CPU_CLOCK_RATE==100000000 /* 100 MHz clock for the MIPS core */
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lw t1, EBU_BUSCON0(t0) /* value set up by magic flash word */
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sw t1, EBU_BUSCON2(t0)
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#else /* 150 MHz or 133 MHz */
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li t1, 0x8841417E
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sw t1, EBU_BUSCON0(t0)
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sw t1, EBU_BUSCON2(t0)
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#endif
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li t1, 0xA0800041
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sw t1, EBU_ADDSEL2(t0)
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/* Need to initialize CS1 too, so as to to prevent overlapping with
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* Flash bank 1.
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*/
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li t1, 0xBE0000F1
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sw t1, EBU_ADDSEL1(t0)
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#if CPU_CLOCK_RATE==100000000 /* 100 MHz clock for the MIPS core */
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li t1, 0x684142BD
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#else /* 150 MHz or 133 MHz */
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li t1, 0x684143FD
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#endif
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sw t1, EBU_BUSCON1(t0)
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#if CPU_CLOCK_RATE==150000000 /* 150 MHz clock for the MIPS core */
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li t0, CGU_MODUL_BASE
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li t1, 0x80000017
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sw t1, CGU_DIVCR(t0)
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li t1, 0xC00B0001
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sw t1, CGU_PLL1CR(t0)
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lui t2, 0x8000
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b1:
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lw t1, CGU_PLL1SR(t0)
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and t1, t1, t2
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beq t1, zero, b1
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li t1, 0x80000001
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sw t1, CGU_MUXCR(t0)
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#elif CPU_CLOCK_RATE==133000000 /* 133 MHz clock for the MIPS core */
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li t0, CGU_MODUL_BASE
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li t1, 0x80000054
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sw t1, CGU_DIVCR(t0)
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li t1, 0x80000000
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sw t1, CGU_MUXCR(t0)
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li t1, 0x800B0001
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sw t1, CGU_PLL1CR(t0)
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#endif
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/* SDRAM Initialization.
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*/
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li t0, MC_MODUL_BASE
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/* Clear Error log registers */
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sw zero, MC_ERRCAUSE(t0)
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sw zero, MC_ERRADDR(t0)
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/* Set clock ratio to 1:1 */
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li t1, 0x03 /* clkrat=1:1, rddel=3 */
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sw t1, MC_IOGP(t0)
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/* Clear Power-down registers */
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sw zero, MC_SELFRFSH(t0)
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/* Set CAS Latency */
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li t1, 0x00000020 /* CL = 2 */
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sw t1, MC_MRSCODE(t0)
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/* Set word width to 16 bit */
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li t1, 0x2
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sw t1, MC_CFGDW(t0)
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/* Set CS0 to SDRAM parameters */
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li t1, 0x000014C9
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sw t1, MC_CFGPB0(t0)
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/* Set SDRAM latency parameters */
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li t1, 0x00026325 /* BC PC100 */
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sw t1, MC_LATENCY(t0)
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/* Set SDRAM refresh rate */
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li t1, 0x00000C30 /* 4K/64ms @ 100MHz */
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sw t1, MC_TREFRESH(t0)
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/* Finally enable the controller */
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li t1, 1
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sw t1, MC_CTRLENA(t0)
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j ra
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nop
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