upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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588 lines
9.2 KiB
588 lines
9.2 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Device Tree file for the Guntermann & Drunck ControlCenter-Compact board
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*
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* Copyright (C) 2016 Mario Six <mario.six@gdsys.cc>
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*
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* based on the Device Tree file for Marvell Armada 388 evaluation board
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* (DB-88F6820), which is
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*
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* Copyright (C) 2014 Marvell
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*
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*/
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/dts-v1/;
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#include "armada-388.dtsi"
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&gpio0 {
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u-boot,dm-pre-reloc;
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};
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&gpio1 {
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u-boot,dm-pre-reloc;
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};
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&uart0 {
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u-boot,dm-pre-reloc;
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};
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&uart1 {
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u-boot,dm-pre-reloc;
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};
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/ {
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model = "Controlcenter Digital Compact";
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compatible = "marvell,a385-db", "marvell,armada388",
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"marvell,armada385", "marvell,armada380";
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chosen {
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bootargs = "console=ttyS1,115200 earlyprintk";
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stdout-path = "/soc/internal-regs/serial@12100";
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};
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aliases {
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ethernet0 = ð0;
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ethernet2 = ð2;
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mdio-gpio0 = &MDIO0;
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mdio-gpio1 = &MDIO1;
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mdio-gpio2 = &MDIO2;
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spi0 = &spi0;
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spi1 = &spi1;
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i2c0 = &I2C0;
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i2c1 = &I2C1;
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x10000000>; /* 256 MB */
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};
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clocks {
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sc16isclk: sc16isclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <11059200>;
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};
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};
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
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internal-regs {
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spi0: spi@10600 {
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status = "okay";
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sc16is741: sc16is741@0 {
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compatible = "nxp,sc16is741";
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reg = <0>;
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clocks = <&sc16isclk>;
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spi-max-frequency = <4000000>;
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interrupt-parent = <&gpio0>;
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interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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spi1: spi@10680 {
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status = "okay";
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u-boot,dm-pre-reloc;
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "n25q016a", "spi-flash";
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reg = <0>; /* Chip select 0 */
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spi-max-frequency = <108000000>;
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};
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spi-flash@1 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "n25q128a11", "spi-flash";
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reg = <1>; /* Chip select 1 */
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spi-max-frequency = <108000000>;
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u-boot,dm-pre-reloc;
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};
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};
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I2C0: i2c@11000 {
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status = "okay";
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clock-frequency = <1000000>;
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u-boot,dm-pre-reloc;
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PCA21: pca9698@21 {
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compatible = "nxp,pca9698";
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reg = <0x21>;
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#gpio-cells = <2>;
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gpio-controller;
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};
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PCA22: pca9698@22 {
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compatible = "nxp,pca9698";
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u-boot,dm-pre-reloc;
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reg = <0x22>;
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#gpio-cells = <2>;
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gpio-controller;
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};
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PCA23: pca9698@23 {
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compatible = "nxp,pca9698";
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reg = <0x23>;
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#gpio-cells = <2>;
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gpio-controller;
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};
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PCA24: pca9698@24 {
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compatible = "nxp,pca9698";
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reg = <0x24>;
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#gpio-cells = <2>;
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gpio-controller;
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};
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PCA25: pca9698@25 {
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compatible = "nxp,pca9698";
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reg = <0x25>;
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#gpio-cells = <2>;
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gpio-controller;
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};
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PCA26: pca9698@26 {
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compatible = "nxp,pca9698";
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reg = <0x26>;
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#gpio-cells = <2>;
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gpio-controller;
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};
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};
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I2C1: i2c@11100 {
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status = "okay";
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clock-frequency = <400000>;
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at97sc3205t@29 {
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compatible = "atmel,at97sc3204t";
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reg = <0x29>;
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u-boot,i2c-offset-len = <0>;
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};
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emc2305@2d {
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compatible = "smsc,emc2305";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x2d>;
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fan@0 {
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reg = <0>;
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};
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fan@1 {
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reg = <1>;
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};
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fan@2 {
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reg = <2>;
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};
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fan@3 {
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reg = <3>;
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};
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fan@4 {
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reg = <4>;
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};
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};
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lm77@48 {
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compatible = "national,lm77";
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reg = <0x48>;
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};
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ads1015@49 {
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compatible = "ti,ads1015";
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reg = <0x49>;
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};
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lm77@4a {
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compatible = "national,lm77";
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reg = <0x4a>;
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};
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ads1015@4b {
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compatible = "ti,ads1015";
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reg = <0x4b>;
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};
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emc2305@4c {
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compatible = "smsc,emc2305";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x4c>;
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fan@0 {
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reg = <0>;
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};
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fan@1 {
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reg = <1>;
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};
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fan@2 {
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reg = <2>;
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};
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fan@3 {
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reg = <3>;
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};
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fan@4 {
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reg = <4>;
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};
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};
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at24c512@54 {
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compatible = "atmel,24c512";
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reg = <0x54>;
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u-boot,i2c-offset-len = <2>;
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};
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ds1339@68 {
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compatible = "dallas,ds1339";
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reg = <0x68>;
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};
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};
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serial@12000 {
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status = "okay";
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};
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serial@12100 {
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status = "okay";
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};
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ethernet@34000 {
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status = "okay";
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phy = <&phy1>;
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phy-mode = "sgmii";
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};
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usb@58000 {
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status = "ok";
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};
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ethernet@70000 {
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status = "okay";
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phy = <&phy0>;
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phy-mode = "sgmii";
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};
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mdio@72004 {
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phy0: ethernet-phy@0 {
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reg = <1>;
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};
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phy1: ethernet-phy@1 {
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reg = <0>;
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};
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};
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sata@a8000 {
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status = "okay";
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};
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sdhci@d8000 {
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broken-cd;
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wp-inverted;
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bus-width = <4>;
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status = "okay";
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no-1-8-v;
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};
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usb3@f0000 {
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status = "okay";
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};
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};
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pcie-controller {
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status = "okay";
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/*
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* The two PCIe units are accessible through
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* standard PCIe slots on the board.
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*/
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pcie@3,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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};
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MDIO0: mdio0 {
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compatible = "virtual,mdio-gpio";
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#address-cells = <1>;
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#size-cells = <0>;
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gpios = < /*MDC*/ &gpio0 13 0
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/*MDIO*/ &gpio0 14 0>;
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mv88e1240@0 {
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reg = <0x0>;
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};
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mv88e1240@1 {
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reg = <0x1>;
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};
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mv88e1240@2 {
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reg = <0x2>;
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};
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mv88e1240@3 {
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reg = <0x3>;
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};
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mv88e1240@4 {
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reg = <0x4>;
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};
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mv88e1240@5 {
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reg = <0x5>;
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};
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mv88e1240@6 {
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reg = <0x6>;
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};
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mv88e1240@7 {
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reg = <0x7>;
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};
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mv88e1240@8 {
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reg = <0x8>;
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};
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mv88e1240@9 {
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reg = <0x9>;
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};
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mv88e1240@a {
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reg = <0xa>;
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};
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mv88e1240@b {
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reg = <0xb>;
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};
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mv88e1240@c {
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reg = <0xc>;
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};
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mv88e1240@d {
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reg = <0xd>;
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};
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mv88e1240@e {
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reg = <0xe>;
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};
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mv88e1240@f {
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reg = <0xf>;
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};
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mv88e1240@10 {
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reg = <0x10>;
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};
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mv88e1240@11 {
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reg = <0x11>;
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};
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mv88e1240@12 {
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reg = <0x12>;
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};
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mv88e1240@13 {
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reg = <0x13>;
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};
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mv88e1240@14 {
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reg = <0x14>;
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};
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mv88e1240@15 {
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reg = <0x15>;
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};
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mv88e1240@16 {
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reg = <0x16>;
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};
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mv88e1240@17 {
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reg = <0x17>;
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};
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mv88e1240@18 {
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reg = <0x18>;
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};
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mv88e1240@19 {
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reg = <0x19>;
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};
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mv88e1240@1a {
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reg = <0x1a>;
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};
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mv88e1240@1b {
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reg = <0x1b>;
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};
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mv88e1240@1c {
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reg = <0x1c>;
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};
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mv88e1240@1d {
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reg = <0x1d>;
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};
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mv88e1240@1e {
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reg = <0x1e>;
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};
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mv88e1240@1f {
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reg = <0x1f>;
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};
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};
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MDIO1: mdio1 {
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compatible = "virtual,mdio-gpio";
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#address-cells = <1>;
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#size-cells = <0>;
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gpios = < /*MDC*/ &gpio0 25 0
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/*MDIO*/ &gpio1 13 0>;
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mv88e1240@0 {
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reg = <0x0>;
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};
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mv88e1240@1 {
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reg = <0x1>;
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};
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mv88e1240@2 {
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reg = <0x2>;
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};
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mv88e1240@3 {
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reg = <0x3>;
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};
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mv88e1240@4 {
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reg = <0x4>;
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};
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mv88e1240@5 {
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reg = <0x5>;
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};
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mv88e1240@6 {
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reg = <0x6>;
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};
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mv88e1240@7 {
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reg = <0x7>;
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};
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mv88e1240@8 {
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reg = <0x8>;
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};
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mv88e1240@9 {
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reg = <0x9>;
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};
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mv88e1240@a {
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reg = <0xa>;
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};
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mv88e1240@b {
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reg = <0xb>;
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};
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mv88e1240@c {
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reg = <0xc>;
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};
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mv88e1240@d {
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reg = <0xd>;
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};
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mv88e1240@e {
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reg = <0xe>;
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};
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mv88e1240@f {
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reg = <0xf>;
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};
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mv88e1240@10 {
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reg = <0x10>;
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};
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mv88e1240@11 {
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reg = <0x11>;
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};
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mv88e1240@12 {
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reg = <0x12>;
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};
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mv88e1240@13 {
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reg = <0x13>;
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};
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mv88e1240@14 {
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reg = <0x14>;
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};
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mv88e1240@15 {
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reg = <0x15>;
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};
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mv88e1240@16 {
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reg = <0x16>;
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};
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mv88e1240@17 {
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reg = <0x17>;
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};
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mv88e1240@18 {
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reg = <0x18>;
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};
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mv88e1240@19 {
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reg = <0x19>;
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};
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mv88e1240@1a {
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reg = <0x1a>;
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};
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mv88e1240@1b {
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reg = <0x1b>;
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};
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mv88e1240@1c {
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reg = <0x1c>;
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};
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mv88e1240@1d {
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reg = <0x1d>;
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};
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mv88e1240@1e {
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reg = <0x1e>;
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};
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mv88e1240@1f {
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reg = <0x1f>;
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};
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};
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MDIO2: mdio2 {
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compatible = "virtual,mdio-gpio";
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#address-cells = <1>;
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#size-cells = <0>;
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gpios = < /*MDC*/ &gpio1 14 0
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/*MDIO*/ &gpio0 24 0>;
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mv88e1240@0 {
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reg = <0x0>;
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};
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mv88e1240@1 {
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reg = <0x1>;
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};
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mv88e1240@2 {
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reg = <0x2>;
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};
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mv88e1240@3 {
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reg = <0x3>;
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};
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mv88e1240@4 {
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reg = <0x4>;
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};
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mv88e1240@5 {
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reg = <0x5>;
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};
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mv88e1240@6 {
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reg = <0x6>;
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};
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mv88e1240@7 {
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reg = <0x7>;
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};
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mv88e1240@8 {
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reg = <0x8>;
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};
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mv88e1240@9 {
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reg = <0x9>;
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};
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mv88e1240@a {
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reg = <0xa>;
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};
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mv88e1240@b {
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reg = <0xb>;
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};
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mv88e1240@c {
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reg = <0xc>;
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};
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mv88e1240@d {
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reg = <0xd>;
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};
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mv88e1240@e {
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reg = <0xe>;
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};
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mv88e1240@f {
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reg = <0xf>;
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};
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mv88e1240@10 {
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reg = <0x10>;
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};
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mv88e1240@11 {
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reg = <0x11>;
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};
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mv88e1240@12 {
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reg = <0x12>;
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};
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mv88e1240@13 {
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reg = <0x13>;
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};
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mv88e1240@14 {
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reg = <0x14>;
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};
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mv88e1240@15 {
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reg = <0x15>;
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};
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};
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};
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leds {
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compatible = "gpio-leds";
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finder_led {
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label = "finder-led";
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gpios = <&PCA22 25 0>;
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};
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status_led {
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label = "status-led";
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gpios = <&gpio0 29 0>;
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};
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};
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};
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