upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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370 lines
7.9 KiB
370 lines
7.9 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2012 Samsung Electronics
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* R. Chandrasekar <rcsekar@samsung.com>
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*/
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#include <asm/arch/clk.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/i2s-regs.h>
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#include <asm/io.h>
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#include <common.h>
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#include <sound.h>
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#include <i2s.h>
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#define FIC_TX2COUNT(x) (((x) >> 24) & 0xf)
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#define FIC_TX1COUNT(x) (((x) >> 16) & 0xf)
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#define FIC_TXCOUNT(x) (((x) >> 8) & 0xf)
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#define FIC_RXCOUNT(x) (((x) >> 0) & 0xf)
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#define FICS_TXCOUNT(x) (((x) >> 8) & 0x7f)
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#define TIMEOUT_I2S_TX 100 /* i2s transfer timeout */
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/*
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* Sets the frame size for I2S LR clock
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*
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* @param i2s_reg i2s regiter address
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* @param rfs Frame Size
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*/
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static void i2s_set_lr_framesize(struct i2s_reg *i2s_reg, unsigned int rfs)
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{
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unsigned int mod = readl(&i2s_reg->mod);
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mod &= ~MOD_RCLK_MASK;
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switch (rfs) {
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case 768:
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mod |= MOD_RCLK_768FS;
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break;
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case 512:
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mod |= MOD_RCLK_512FS;
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break;
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case 384:
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mod |= MOD_RCLK_384FS;
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break;
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default:
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mod |= MOD_RCLK_256FS;
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break;
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}
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writel(mod, &i2s_reg->mod);
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}
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/*
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* Sets the i2s transfer control
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*
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* @param i2s_reg i2s regiter address
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* @param on 1 enable tx , 0 disable tx transfer
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*/
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static void i2s_txctrl(struct i2s_reg *i2s_reg, int on)
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{
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unsigned int con = readl(&i2s_reg->con);
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unsigned int mod = readl(&i2s_reg->mod) & ~MOD_MASK;
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if (on) {
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con |= CON_ACTIVE;
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con &= ~CON_TXCH_PAUSE;
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} else {
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con |= CON_TXCH_PAUSE;
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con &= ~CON_ACTIVE;
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}
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writel(mod, &i2s_reg->mod);
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writel(con, &i2s_reg->con);
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}
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/*
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* set the bit clock frame size (in multiples of LRCLK)
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*
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* @param i2s_reg i2s regiter address
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* @param bfs bit Frame Size
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*/
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static void i2s_set_bitclk_framesize(struct i2s_reg *i2s_reg, unsigned bfs)
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{
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unsigned int mod = readl(&i2s_reg->mod);
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mod &= ~MOD_BCLK_MASK;
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switch (bfs) {
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case 48:
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mod |= MOD_BCLK_48FS;
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break;
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case 32:
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mod |= MOD_BCLK_32FS;
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break;
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case 24:
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mod |= MOD_BCLK_24FS;
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break;
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case 16:
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mod |= MOD_BCLK_16FS;
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break;
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default:
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return;
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}
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writel(mod, &i2s_reg->mod);
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}
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/*
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* flushes the i2stx fifo
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*
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* @param i2s_reg i2s regiter address
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* @param flush Tx fifo flush command (0x00 - do not flush
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* 0x80 - flush tx fifo)
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*/
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void i2s_fifo(struct i2s_reg *i2s_reg, unsigned int flush)
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{
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/* Flush the FIFO */
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setbits_le32(&i2s_reg->fic, flush);
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clrbits_le32(&i2s_reg->fic, flush);
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}
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/*
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* Set System Clock direction
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*
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* @param i2s_reg i2s regiter address
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* @param dir Clock direction
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*
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* @return int value 0 for success, -1 in case of error
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*/
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int i2s_set_sysclk_dir(struct i2s_reg *i2s_reg, int dir)
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{
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unsigned int mod = readl(&i2s_reg->mod);
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if (dir == SND_SOC_CLOCK_IN)
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mod |= MOD_CDCLKCON;
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else
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mod &= ~MOD_CDCLKCON;
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writel(mod, &i2s_reg->mod);
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return 0;
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}
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/*
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* Sets I2S Clcok format
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*
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* @param fmt i2s clock properties
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* @param i2s_reg i2s regiter address
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*
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* @return int value 0 for success, -1 in case of error
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*/
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int i2s_set_fmt(struct i2s_reg *i2s_reg, unsigned int fmt)
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{
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unsigned int mod = readl(&i2s_reg->mod);
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unsigned int tmp = 0;
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unsigned int ret = 0;
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/* Format is priority */
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_RIGHT_J:
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tmp |= MOD_LR_RLOW;
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tmp |= MOD_SDF_MSB;
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break;
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case SND_SOC_DAIFMT_LEFT_J:
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tmp |= MOD_LR_RLOW;
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tmp |= MOD_SDF_LSB;
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break;
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case SND_SOC_DAIFMT_I2S:
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tmp |= MOD_SDF_IIS;
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break;
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default:
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debug("%s: Invalid format priority [0x%x]\n", __func__,
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(fmt & SND_SOC_DAIFMT_FORMAT_MASK));
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return -1;
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}
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/*
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* INV flag is relative to the FORMAT flag - if set it simply
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* flips the polarity specified by the Standard
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*/
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_NB_NF:
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break;
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case SND_SOC_DAIFMT_NB_IF:
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if (tmp & MOD_LR_RLOW)
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tmp &= ~MOD_LR_RLOW;
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else
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tmp |= MOD_LR_RLOW;
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break;
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default:
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debug("%s: Invalid clock ploarity input [0x%x]\n", __func__,
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(fmt & SND_SOC_DAIFMT_INV_MASK));
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return -1;
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}
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBS_CFS:
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tmp |= MOD_SLAVE;
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break;
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case SND_SOC_DAIFMT_CBM_CFM:
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/* Set default source clock in Master mode */
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ret = i2s_set_sysclk_dir(i2s_reg, SND_SOC_CLOCK_OUT);
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if (ret != 0) {
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debug("%s:set i2s clock direction failed\n", __func__);
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return -1;
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}
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break;
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default:
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debug("%s: Invalid master selection [0x%x]\n", __func__,
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(fmt & SND_SOC_DAIFMT_MASTER_MASK));
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return -1;
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}
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mod &= ~(MOD_SDF_MASK | MOD_LR_RLOW | MOD_SLAVE);
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mod |= tmp;
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writel(mod, &i2s_reg->mod);
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return 0;
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}
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/*
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* Sets the sample width in bits
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*
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* @param blc samplewidth (size of sample in bits)
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* @param i2s_reg i2s regiter address
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*
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* @return int value 0 for success, -1 in case of error
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*/
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int i2s_set_samplesize(struct i2s_reg *i2s_reg, unsigned int blc)
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{
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unsigned int mod = readl(&i2s_reg->mod);
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mod &= ~MOD_BLCP_MASK;
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mod &= ~MOD_BLC_MASK;
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switch (blc) {
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case 8:
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mod |= MOD_BLCP_8BIT;
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mod |= MOD_BLC_8BIT;
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break;
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case 16:
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mod |= MOD_BLCP_16BIT;
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mod |= MOD_BLC_16BIT;
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break;
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case 24:
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mod |= MOD_BLCP_24BIT;
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mod |= MOD_BLC_24BIT;
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break;
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default:
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debug("%s: Invalid sample size input [0x%x]\n",
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__func__, blc);
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return -1;
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}
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writel(mod, &i2s_reg->mod);
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return 0;
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}
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int i2s_transfer_tx_data(struct i2stx_info *pi2s_tx, unsigned int *data,
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unsigned long data_size)
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{
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int i;
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int start;
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struct i2s_reg *i2s_reg =
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(struct i2s_reg *)pi2s_tx->base_address;
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if (data_size < FIFO_LENGTH) {
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debug("%s : Invalid data size\n", __func__);
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return -1; /* invalid pcm data size */
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}
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/* fill the tx buffer before stating the tx transmit */
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for (i = 0; i < FIFO_LENGTH; i++)
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writel(*data++, &i2s_reg->txd);
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data_size -= FIFO_LENGTH;
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i2s_txctrl(i2s_reg, I2S_TX_ON);
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while (data_size > 0) {
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start = get_timer(0);
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if (!(CON_TXFIFO_FULL & (readl(&i2s_reg->con)))) {
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writel(*data++, &i2s_reg->txd);
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data_size--;
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} else {
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if (get_timer(start) > TIMEOUT_I2S_TX) {
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i2s_txctrl(i2s_reg, I2S_TX_OFF);
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debug("%s: I2S Transfer Timeout\n", __func__);
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return -1;
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}
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}
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}
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i2s_txctrl(i2s_reg, I2S_TX_OFF);
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return 0;
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}
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int i2s_tx_init(struct i2stx_info *pi2s_tx)
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{
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int ret;
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struct i2s_reg *i2s_reg =
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(struct i2s_reg *)pi2s_tx->base_address;
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if (pi2s_tx->id == 0) {
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/* Initialize GPIO for I2S-0 */
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exynos_pinmux_config(PERIPH_ID_I2S0, 0);
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/* Set EPLL Clock */
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ret = set_epll_clk(pi2s_tx->samplingrate * pi2s_tx->rfs * 4);
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} else if (pi2s_tx->id == 1) {
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/* Initialize GPIO for I2S-1 */
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exynos_pinmux_config(PERIPH_ID_I2S1, 0);
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/* Set EPLL Clock */
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ret = set_epll_clk(pi2s_tx->audio_pll_clk);
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} else {
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debug("%s: unsupported i2s-%d bus\n", __func__, pi2s_tx->id);
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return -1;
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}
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if (ret != 0) {
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debug("%s: epll clock set rate failed\n", __func__);
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return -1;
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}
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/* Select Clk Source for Audio 0 or 1 */
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ret = set_i2s_clk_source(pi2s_tx->id);
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if (ret == -1) {
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debug("%s: unsupported clock for i2s-%d\n", __func__,
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pi2s_tx->id);
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return -1;
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}
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if (pi2s_tx->id == 0) {
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/*Reset the i2s module */
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writel(CON_RESET, &i2s_reg->con);
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writel(MOD_OP_CLK | MOD_RCLKSRC, &i2s_reg->mod);
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/* set i2s prescaler */
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writel(PSREN | PSVAL, &i2s_reg->psr);
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} else {
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/* Set Prescaler to get MCLK */
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ret = set_i2s_clk_prescaler(pi2s_tx->audio_pll_clk,
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(pi2s_tx->samplingrate * (pi2s_tx->rfs)),
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pi2s_tx->id);
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}
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if (ret == -1) {
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debug("%s: unsupported prescalar for i2s-%d\n", __func__,
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pi2s_tx->id);
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return -1;
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}
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/* Configure I2s format */
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ret = i2s_set_fmt(i2s_reg, (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
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SND_SOC_DAIFMT_CBM_CFM));
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if (ret == 0) {
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i2s_set_lr_framesize(i2s_reg, pi2s_tx->rfs);
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ret = i2s_set_samplesize(i2s_reg, pi2s_tx->bitspersample);
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if (ret != 0) {
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debug("%s:set sample rate failed\n", __func__);
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return -1;
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}
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i2s_set_bitclk_framesize(i2s_reg, pi2s_tx->bfs);
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/* disable i2s transfer flag and flush the fifo */
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i2s_txctrl(i2s_reg, I2S_TX_OFF);
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i2s_fifo(i2s_reg, FIC_TXFLUSH);
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} else {
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debug("%s: failed\n", __func__);
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}
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return ret;
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}
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