upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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68 lines
1.9 KiB
68 lines
1.9 KiB
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright 2008-2014 Freescale Semiconductor, Inc.
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*/
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#ifndef COMMON_TIMING_PARAMS_H
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#define COMMON_TIMING_PARAMS_H
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typedef struct {
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/* parameters to constrict */
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unsigned int tckmin_x_ps;
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unsigned int tckmax_ps;
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unsigned int trcd_ps;
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unsigned int trp_ps;
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unsigned int tras_ps;
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#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
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unsigned int taamin_ps;
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#endif
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#ifdef CONFIG_SYS_FSL_DDR4
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unsigned int trfc1_ps;
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unsigned int trfc2_ps;
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unsigned int trfc4_ps;
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unsigned int trrds_ps;
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unsigned int trrdl_ps;
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unsigned int tccdl_ps;
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unsigned int trfc_slr_ps;
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#else
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unsigned int twtr_ps; /* maximum = 63750 ps */
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unsigned int trfc_ps; /* maximum = 255 ns + 256 ns + .75 ns
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= 511750 ps */
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unsigned int trrd_ps; /* maximum = 63750 ps */
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unsigned int trtp_ps; /* byte 38, spd->trtp */
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#endif
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unsigned int twr_ps; /* maximum = 63750 ps */
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unsigned int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */
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unsigned int refresh_rate_ps;
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unsigned int extended_op_srt;
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#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
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unsigned int tis_ps; /* byte 32, spd->ca_setup */
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unsigned int tih_ps; /* byte 33, spd->ca_hold */
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unsigned int tds_ps; /* byte 34, spd->data_setup */
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unsigned int tdh_ps; /* byte 35, spd->data_hold */
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unsigned int tdqsq_max_ps; /* byte 44, spd->tdqsq */
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unsigned int tqhs_ps; /* byte 45, spd->tqhs */
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#endif
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unsigned int ndimms_present;
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unsigned int lowest_common_spd_caslat;
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unsigned int highest_common_derated_caslat;
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unsigned int additive_latency;
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unsigned int all_dimms_burst_lengths_bitmask;
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unsigned int all_dimms_registered;
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unsigned int all_dimms_unbuffered;
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unsigned int all_dimms_ecc_capable;
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unsigned long long total_mem;
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unsigned long long base_address;
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/* DDR3 RDIMM */
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unsigned char rcw[16]; /* Register Control Word 0-15 */
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} common_timing_params_t;
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#endif
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