upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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72 lines
2.2 KiB
72 lines
2.2 KiB
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2013 Keymile AG
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* Valentin Longchamp <valentin.longchamp@keymile.com>
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* KMLION1 */
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#if defined(CONFIG_KMLION1)
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#define CONFIG_HOSTNAME "kmlion1"
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#define CONFIG_KM_BOARD_NAME "kmlion1"
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/* KMCOGE4 */
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#elif defined(CONFIG_KMCOGE4)
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#define CONFIG_HOSTNAME "kmcoge4"
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#define CONFIG_KM_BOARD_NAME "kmcoge4"
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#else
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#error ("Board not supported")
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#endif
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#define CONFIG_KMP204X
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#include "km/kmp204x-common.h"
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#if defined(CONFIG_KMLION1)
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/* App1 Local bus */
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#define CONFIG_SYS_LBAPP1_BASE 0xD0000000
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#define CONFIG_SYS_LBAPP1_BASE_PHYS 0xFD0000000ull
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#define CONFIG_SYS_LBAPP1_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBAPP1_BASE_PHYS) \
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| BR_PS_8 /* Port Size 8 bits */ \
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| BR_DECC_OFF /* no error corr */ \
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| BR_MS_GPCM /* MSEL = GPCM */ \
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| BR_V) /* valid */
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#define CONFIG_SYS_LBAPP1_OR_PRELIM (OR_AM_256MB /* length 256MB */ \
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| OR_GPCM_ACS_DIV2 /* LCS 1/2 clk after */ \
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| OR_GPCM_CSNT /* LCS 1/4 clk before */ \
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| OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
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| OR_GPCM_TRLX /* relaxed tmgs */ \
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| OR_GPCM_EAD) /* extra bus clk cycles */
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/* Local bus app1 Base Address */
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#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_LBAPP1_BR_PRELIM
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/* Local bus app1 Options */
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#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_LBAPP1_OR_PRELIM
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#endif
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/* App2 Local bus */
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#define CONFIG_SYS_LBAPP2_BASE 0xE0000000
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#define CONFIG_SYS_LBAPP2_BASE_PHYS 0xFE0000000ull
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#define CONFIG_SYS_LBAPP2_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBAPP2_BASE_PHYS) \
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| BR_PS_8 /* Port Size 8 bits */ \
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| BR_DECC_OFF /* no error corr */ \
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| BR_MS_GPCM /* MSEL = GPCM */ \
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| BR_V) /* valid */
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#define CONFIG_SYS_LBAPP2_OR_PRELIM (OR_AM_256MB /* length 256MB */ \
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| OR_GPCM_ACS_DIV2 /* LCS 1/2 clk after */ \
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| OR_GPCM_CSNT /* LCS 1/4 clk before */ \
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| OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
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| OR_GPCM_TRLX /* relaxed tmgs */ \
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| OR_GPCM_EAD) /* extra bus clk cycles */
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/* Local bus app2 Base Address */
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#define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_LBAPP2_BR_PRELIM
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/* Local bus app2 Options */
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#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_LBAPP2_OR_PRELIM
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#endif /* __CONFIG_H */
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