upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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61 lines
2.8 KiB
61 lines
2.8 KiB
Intel Interrupt Router Device Binding
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=====================================
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The device tree node which describes the operation of the Intel Interrupt Router
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device is as follows:
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Required properties :
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- reg : Specifies the interrupt router's PCI configuration space address as
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defined by the Open Firmware spec.
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- compatible = "intel,irq-router"
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- intel,pirq-config : Specifies the IRQ routing register programming mechanism.
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Valid values are:
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"pci": IRQ routing is controlled by PCI configuration registers
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"ibase": IRQ routing is in the memory-mapped IBASE register block
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- intel,ibase-offset : IBASE register offset in the interrupt router's PCI
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configuration space, required only if intel,pirq-config = "ibase".
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- intel,actl-8bit : If ACTL (ACPI control) register width is 8-bit, this must
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be specified. The 8-bit ACTL register is seen on ICH series chipset, like
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ICH9/Panther Point/etc. On Atom chipset it is a 32-bit register.
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- intel,actl-addr : ACTL (ACPI control) register offset. ACTL can be either
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in the interrupt router's PCI configuration space, or IBASE.
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- intel,pirq-link : Specifies the PIRQ link information with two cells. The
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first cell is the register offset that controls the first PIRQ link routing.
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The second cell is the total number of PIRQ links the router supports.
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- intel,pirq-regmap : Specifies PIRQ routing register offset of all PIRQ links,
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encoded as 2 cells a group for each link. The first cell is the PIRQ link
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number (0 for PIRQA, 1 for PIRQB, etc). The second cell is the PIRQ routing
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register offset from the interrupt router's base address. If this property
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is omitted, it indicates a consecutive register offset from the first PIRQ
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link, as specified by the first cell of intel,pirq-link.
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- intel,pirq-mask : Specifies the IRQ mask representing the 16 IRQs in the
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8259 PIC. Bit N is 1 means IRQ N is available to be routed.
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- intel,pirq-routing : Specifies all PCI devices' IRQ routing information,
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encoded as 3 cells a group for a device. The first cell is the device's PCI
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bus number, device number and function number encoding with PCI_BDF() macro.
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The second cell is the PCI interrupt pin used by this device. The last cell
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is which PIRQ line the PCI interrupt pin is routed to.
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Example
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-------
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#include <dt-bindings/interrupt-router/intel-irq.h>
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irq-router@1f,0 {
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reg = <0x0000f800 0 0 0 0>;
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compatible = "intel,irq-router";
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intel,pirq-config = "pci";
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intel,pirq-link = <0x60 8>;
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intel,pirq-mask = <0xdef8>;
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intel,pirq-routing = <
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PCI_BDF(0, 2, 0) INTA PIRQA
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PCI_BDF(0, 3, 0) INTA PIRQB
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PCI_BDF(0, 8, 0) INTA PIRQC
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PCI_BDF(0, 8, 1) INTB PIRQD
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PCI_BDF(1, 6, 0) INTA PIRQE
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PCI_BDF(1, 6, 1) INTB PIRQF
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PCI_BDF(1, 6, 2) INTC PIRQG
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PCI_BDF(1, 6, 3) INTD PIRQH
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>;
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};
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