upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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289 lines
9.7 KiB
289 lines
9.7 KiB
/*
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* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <spd_sdram.h>
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#define BOOT_SMALL_FLASH 32 /* 00100000 */
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#define FLASH_ONBD_N 2 /* 00000010 */
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#define FLASH_SRAM_SEL 1 /* 00000001 */
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DECLARE_GLOBAL_DATA_PTR;
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long int fixed_sdram(void);
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int board_early_init_f(void)
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{
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uint reg;
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unsigned char *fpga_base = (unsigned char *)CFG_FPGA_BASE;
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unsigned char status;
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/*--------------------------------------------------------------------
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* Setup the external bus controller/chip selects
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*-------------------------------------------------------------------*/
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mtdcr(ebccfga, xbcfg);
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reg = mfdcr(ebccfgd);
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mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
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mtebc(pb1ap, 0x02815480); /* NVRAM/RTC */
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mtebc(pb1cr, 0x48018000); /* BA=0x480 1MB R/W 8-bit */
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mtebc(pb7ap, 0x01015280); /* FPGA registers */
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mtebc(pb7cr, 0x48318000); /* BA=0x483 1MB R/W 8-bit */
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/* read FPGA_REG0 and set the bus controller */
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status = *fpga_base;
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if ((status & BOOT_SMALL_FLASH) && !(status & FLASH_ONBD_N)) {
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mtebc(pb0ap, 0x9b015480); /* FLASH/SRAM */
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mtebc(pb0cr, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */
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mtebc(pb2ap, 0x9b015480); /* 4MB FLASH */
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mtebc(pb2cr, 0xff858000); /* BAS=0xff8 4MB R/W 8-bit */
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} else {
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mtebc(pb0ap, 0x9b015480); /* 4MB FLASH */
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mtebc(pb0cr, 0xffc58000); /* BAS=0xffc 4MB R/W 8-bit */
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/* set CS2 if FLASH_ONBD_N == 0 */
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if (!(status & FLASH_ONBD_N)) {
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mtebc(pb2ap, 0x9b015480); /* FLASH/SRAM */
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mtebc(pb2cr, 0xff818000); /* BAS=0xff8 4MB R/W 8-bit */
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}
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}
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/*--------------------------------------------------------------------
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* Setup the interrupt controller polarities, triggers, etc.
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*-------------------------------------------------------------------*/
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mtdcr(uic0sr, 0xffffffff); /* clear all */
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mtdcr(uic0er, 0x00000000); /* disable all */
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mtdcr(uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
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mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
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mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
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mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr(uic0sr, 0xffffffff); /* clear all */
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mtdcr(uic1sr, 0xffffffff); /* clear all */
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mtdcr(uic1er, 0x00000000); /* disable all */
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mtdcr(uic1cr, 0x00000000); /* all non-critical */
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mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
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mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
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mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr(uic1sr, 0xffffffff); /* clear all */
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return 0;
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}
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int checkboard(void)
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{
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char *s = getenv("serial#");
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printf("Board: Ebony - AMCC PPC440GP Evaluation Board");
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if (s != NULL) {
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puts(", serial# ");
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puts(s);
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}
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putc('\n');
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return (0);
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}
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long int initdram(int board_type)
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{
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long dram_size = 0;
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#if defined(CONFIG_SPD_EEPROM)
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dram_size = spd_sdram();
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#else
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dram_size = fixed_sdram();
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#endif
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return dram_size;
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}
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#if defined(CFG_DRAM_TEST)
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int testdram(void)
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{
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uint *pstart = (uint *) 0x00000000;
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uint *pend = (uint *) 0x08000000;
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uint *p;
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for (p = pstart; p < pend; p++)
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*p = 0xaaaaaaaa;
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for (p = pstart; p < pend; p++) {
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if (*p != 0xaaaaaaaa) {
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printf("SDRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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for (p = pstart; p < pend; p++)
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*p = 0x55555555;
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for (p = pstart; p < pend; p++) {
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if (*p != 0x55555555) {
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printf("SDRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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return 0;
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}
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#endif
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#if !defined(CONFIG_SPD_EEPROM)
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/*************************************************************************
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* fixed sdram init -- doesn't use serial presence detect.
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*
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* Assumes: 128 MB, non-ECC, non-registered
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* PLB @ 133 MHz
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*
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************************************************************************/
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long int fixed_sdram(void)
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{
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uint reg;
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/*--------------------------------------------------------------------
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* Setup some default
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*------------------------------------------------------------------*/
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mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
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mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
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mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
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mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
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mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
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/*--------------------------------------------------------------------
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* Setup for board-specific specific mem
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*------------------------------------------------------------------*/
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/*
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* Following for CAS Latency = 2.5 @ 133 MHz PLB
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*/
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mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
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mtsdram(mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
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/* RA=10 RD=3 */
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mtsdram(mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
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mtsdram(mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
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mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
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udelay(400); /* Delay 200 usecs (min) */
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/*--------------------------------------------------------------------
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* Enable the controller, then wait for DCEN to complete
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*------------------------------------------------------------------*/
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mtsdram(mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
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for (;;) {
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mfsdram(mem_mcsts, reg);
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if (reg & 0x80000000)
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break;
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}
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return (128 * 1024 * 1024); /* 128 MB */
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}
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#endif /* !defined(CONFIG_SPD_EEPROM) */
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/*************************************************************************
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* pci_pre_init
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*
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* This routine is called just prior to registering the hose and gives
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* the board the opportunity to check things. Returning a value of zero
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* indicates that things are bad & PCI initialization should be aborted.
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*
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* Different boards may wish to customize the pci controller structure
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* (add regions, override default access routines, etc) or perform
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* certain pre-initialization actions.
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*
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************************************************************************/
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#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
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int pci_pre_init(struct pci_controller *hose)
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{
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unsigned long strap;
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/*--------------------------------------------------------------------------+
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* The ebony board is always configured as the host & requires the
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* PCI arbiter to be enabled.
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*--------------------------------------------------------------------------*/
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strap = mfdcr(cpc0_strp1);
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if ((strap & 0x00100000) == 0) {
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printf("PCI: CPC0_STRP1[PAE] not set.\n");
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return 0;
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}
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return 1;
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}
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#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
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/*************************************************************************
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* pci_target_init
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*
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* The bootstrap configuration provides default settings for the pci
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* inbound map (PIM). But the bootstrap config choices are limited and
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* may not be sufficient for a given board.
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*
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************************************************************************/
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#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
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void pci_target_init(struct pci_controller *hose)
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{
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/*--------------------------------------------------------------------------+
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* Disable everything
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*--------------------------------------------------------------------------*/
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out32r(PCIX0_PIM0SA, 0); /* disable */
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out32r(PCIX0_PIM1SA, 0); /* disable */
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out32r(PCIX0_PIM2SA, 0); /* disable */
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out32r(PCIX0_EROMBA, 0); /* disable expansion rom */
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/*--------------------------------------------------------------------------+
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* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
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* options to not support sizes such as 128/256 MB.
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*--------------------------------------------------------------------------*/
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out32r(PCIX0_PIM0LAL, CFG_SDRAM_BASE);
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out32r(PCIX0_PIM0LAH, 0);
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out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
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out32r(PCIX0_BAR0, 0);
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/*--------------------------------------------------------------------------+
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* Program the board's subsystem id/vendor id
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*--------------------------------------------------------------------------*/
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out16r(PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
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out16r(PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
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out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
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}
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#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
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/*************************************************************************
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* is_pci_host
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*
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* This routine is called to determine if a pci scan should be
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* performed. With various hardware environments (especially cPCI and
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* PPMC) it's insufficient to depend on the state of the arbiter enable
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* bit in the strap register, or generic host/adapter assumptions.
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*
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* Rather than hard-code a bad assumption in the general 440 code, the
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* 440 pci code requires the board to decide at runtime.
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*
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* Return 0 for adapter mode, non-zero for host (monarch) mode.
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*
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*
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************************************************************************/
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#if defined(CONFIG_PCI)
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int is_pci_host(struct pci_controller *hose)
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{
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/* The ebony board is always configured as host. */
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return (1);
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}
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#endif /* defined(CONFIG_PCI) */
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