upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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226 lines
6.8 KiB
226 lines
6.8 KiB
/*
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* Copyright (C) 2014 Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __LS2_COMMON_H
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#define __LS2_COMMON_H
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#define CONFIG_SYS_GENERIC_BOARD
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#define CONFIG_REMAKE_ELF
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#define CONFIG_FSL_LSCH3
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#define CONFIG_LS2085A
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#define CONFIG_GICV3
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/* Link Definitions */
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#define CONFIG_SYS_TEXT_BASE 0x30000000
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_SUPPORT_RAW_INITRD
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_BOARD_EARLY_INIT_F 1
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#define CONFIG_IDENT_STRING " LS2085A-EMU"
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#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-EMU"
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/* Flat Device Tree Definitions */
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#define CONFIG_OF_LIBFDT
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#define CONFIG_OF_BOARD_SETUP
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/* new uImage format support */
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#define CONFIG_FIT
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#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
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#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
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#ifndef CONFIG_SYS_FSL_DDR4
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#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
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#define CONFIG_SYS_DDR_RAW_TIMING
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#endif
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#define CONFIG_DIMM_SLOTS_PER_CTLR 1
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#define CONFIG_CHIP_SELECTS_PER_CTRL 4
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#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
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/* SMP Definitions */
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#define CPU_RELEASE_ADDR CONFIG_SYS_INIT_SP_ADDR
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
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#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
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/* Generic Timer Definitions */
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#define COUNTER_FREQUENCY 12000000 /* 12MHz */
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
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/* I2C */
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#define CONFIG_CMD_I2C
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MXC
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#define CONFIG_SYS_MXC_I2C1_SPEED 40000000
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#define CONFIG_SYS_MXC_I2C2_SPEED 40000000
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/* Serial Port */
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#define CONFIG_CONS_INDEX 2
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/* IFC */
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#define CONFIG_FSL_IFC
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#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
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#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
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/*
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* During booting, CS0 needs to be at the region of 0x30000000, i.e. the IFC
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* address 0. But this region is limited to 256MB. To accommodate bigger NOR
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* flash and other devices, we will map CS0 to 0x580000000 after relocation.
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* CONFIG_SYS_FLASH_BASE has the final address (core view)
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* CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
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* CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
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* CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
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*/
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#define CONFIG_SYS_FLASH_BASE 0x580000000ULL
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#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
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#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
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/*
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* NOR Flash Timing Params
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*/
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#define CONFIG_SYS_NOR0_CSPR \
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(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
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CSPR_PORT_SIZE_16 | \
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CSPR_MSEL_NOR | \
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CSPR_V)
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#define CONFIG_SYS_NOR0_CSPR_EARLY \
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(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
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CSPR_PORT_SIZE_16 | \
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CSPR_MSEL_NOR | \
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CSPR_V)
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#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
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#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
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FTIM0_NOR_TEADC(0x1) | \
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FTIM0_NOR_TEAHC(0x1))
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#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
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FTIM1_NOR_TRAD_NOR(0x1))
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#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
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FTIM2_NOR_TCH(0x0) | \
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FTIM2_NOR_TWP(0x1))
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#define CONFIG_SYS_NOR_FTIM3 0x04000000
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#define CONFIG_SYS_IFC_CCR 0x01000000
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#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
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#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
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#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
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#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
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#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
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#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
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#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
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#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
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#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
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/* MC firmware */
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#define CONFIG_FSL_MC_ENET
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#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
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#define CONFIG_SYS_LS_MC_FW_IN_NOR
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#define CONFIG_SYS_LS_MC_FW_ADDR 0x580200000ULL
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/* TODO Actual FW length needs to be determined at runtime from FW header */
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#define CONFIG_SYS_LS_MC_FW_LENGTH (4U * 1024 * 1024)
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#define CONFIG_SYS_LS_MC_DPL_IN_NOR
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#define CONFIG_SYS_LS_MC_DPL_ADDR 0x5806C0000ULL
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/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
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#define CONFIG_SYS_LS_MC_DPL_LENGTH 4096
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#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0xe00000
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/* Carve the MC private DRAM block from the end of DRAM */
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#ifdef CONFIG_FSL_MC_ENET
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#define CONFIG_SYS_MEM_TOP_HIDE mc_get_dram_block_size()
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#endif
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/* Command line configuration */
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_BDI
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_ENV
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#define CONFIG_CMD_FLASH
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#define CONFIG_CMD_IMI
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#define CONFIG_CMD_MEMORY
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_SAVEENV
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#define CONFIG_CMD_RUN
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#define CONFIG_CMD_BOOTD
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#define CONFIG_CMD_ECHO
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#define CONFIG_CMD_SOURCE
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#define CONFIG_CMD_FAT
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#define CONFIG_DOS_PARTITION
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
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/* Physical Memory Map */
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/* fixme: these need to be checked against the board */
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#define CONFIG_CHIP_SELECTS_PER_CTRL 4
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#define CONFIG_SYS_CLK_FREQ 133333333
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#define CONFIG_NR_DRAM_BANKS 2
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_HWCONFIG
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#define HWCONFIG_BUFFER_SIZE 128
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#define CONFIG_DISPLAY_CPUINFO
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/* Initial environment variables */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"hwconfig=fsl_ddr:bank_intlv=auto\0" \
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"loadaddr=0x80100000\0" \
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"kernel_addr=0x100000\0" \
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"ramdisk_addr=0x800000\0" \
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"ramdisk_size=0x2000000\0" \
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"fdt_high=0xffffffffffffffff\0" \
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"initrd_high=0xffffffffffffffff\0" \
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"kernel_start=0x581200000\0" \
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"kernel_load=0x806f0000\0" \
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"kernel_size=0x1000000\0" \
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"console=ttyAMA0,38400n8\0"
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#define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \
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"earlyprintk=uart8250-8bit,0x21c0600"
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#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
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"$kernel_size && bootm $kernel_load"
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#define CONFIG_BOOTDELAY 1
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/* Store environment at top of flash */
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#define CONFIG_ENV_IS_NOWHERE 1
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#define CONFIG_ENV_SIZE 0x1000
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/* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PROMPT "> "
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_CMDLINE_EDITING 1
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#define CONFIG_SYS_MAXARGS 64 /* max command args */
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#ifndef __ASSEMBLY__
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unsigned long mc_get_dram_block_size(void);
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#endif
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#endif /* __LS2_COMMON_H */
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