upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
29 lines
693 B
29 lines
693 B
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
/*
|
|
* Tegra pulse width frequency modulator definitions
|
|
*
|
|
* Copyright (c) 2011 The Chromium OS Authors.
|
|
*/
|
|
|
|
#ifndef __ASM_ARCH_TEGRA_PWM_H
|
|
#define __ASM_ARCH_TEGRA_PWM_H
|
|
|
|
/* This is a single PWM channel */
|
|
struct pwm_ctlr {
|
|
uint control; /* Control register */
|
|
uint reserved[3]; /* Space space */
|
|
};
|
|
|
|
#define PWM_NUM_CHANNELS 4
|
|
|
|
/* PWM_CONTROLLER_PWM_CSR_0/1/2/3_0 */
|
|
#define PWM_ENABLE_SHIFT 31
|
|
#define PWM_ENABLE_MASK (0x1 << PWM_ENABLE_SHIFT)
|
|
|
|
#define PWM_WIDTH_SHIFT 16
|
|
#define PWM_WIDTH_MASK (0x7FFF << PWM_WIDTH_SHIFT)
|
|
|
|
#define PWM_DIVIDER_SHIFT 0
|
|
#define PWM_DIVIDER_MASK (0x1FFF << PWM_DIVIDER_SHIFT)
|
|
|
|
#endif /* __ASM_ARCH_TEGRA_PWM_H */
|
|
|