upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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133 lines
3.5 KiB
133 lines
3.5 KiB
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2009
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* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
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*/
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#ifndef _SYS_PROTO_H_
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#define _SYS_PROTO_H_
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#include <asm/io.h>
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#include <asm/mach-imx/regs-common.h>
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#include <common.h>
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#include "../arch-imx/cpu.h"
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#define soc_rev() (get_cpu_rev() & 0xFF)
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#define is_soc_rev(rev) (soc_rev() == rev)
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/* returns MXC_CPU_ value */
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#define cpu_type(rev) (((rev) >> 12) & 0xff)
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#define soc_type(rev) (((rev) >> 12) & 0xf0)
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/* both macros return/take MXC_CPU_ constants */
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#define get_cpu_type() (cpu_type(get_cpu_rev()))
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#define get_soc_type() (soc_type(get_cpu_rev()))
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#define is_cpu_type(cpu) (get_cpu_type() == cpu)
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#define is_soc_type(soc) (get_soc_type() == soc)
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#define is_mx6() (is_soc_type(MXC_SOC_MX6))
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#define is_mx7() (is_soc_type(MXC_SOC_MX7))
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#define is_mx8m() (is_soc_type(MXC_SOC_MX8M))
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#define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
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#define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
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#define is_mx6sdl() (is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6DL))
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#define is_mx6dl() (is_cpu_type(MXC_CPU_MX6DL))
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#define is_mx6sx() (is_cpu_type(MXC_CPU_MX6SX))
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#define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL))
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#define is_mx6solo() (is_cpu_type(MXC_CPU_MX6SOLO))
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#define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL))
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#define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL))
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#define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL))
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#define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP))
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#ifdef CONFIG_MX6
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#define IMX6_SRC_GPR10_BMODE BIT(28)
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#define IMX6_BMODE_MASK GENMASK(7, 0)
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#define IMX6_BMODE_SHIFT 4
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#define IMX6_BMODE_EMI_MASK BIT(3)
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#define IMX6_BMODE_EMI_SHIFT 3
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#define IMX6_BMODE_SERIAL_ROM_MASK GENMASK(26, 24)
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#define IMX6_BMODE_SERIAL_ROM_SHIFT 24
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enum imx6_bmode_serial_rom {
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IMX6_BMODE_ECSPI1,
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IMX6_BMODE_ECSPI2,
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IMX6_BMODE_ECSPI3,
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IMX6_BMODE_ECSPI4,
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IMX6_BMODE_ECSPI5,
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IMX6_BMODE_I2C1,
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IMX6_BMODE_I2C2,
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IMX6_BMODE_I2C3,
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};
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enum imx6_bmode_emi {
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IMX6_BMODE_ONENAND,
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IMX6_BMODE_NOR,
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};
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enum imx6_bmode {
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IMX6_BMODE_EMI,
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#if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
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IMX6_BMODE_QSPI,
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IMX6_BMODE_RESERVED,
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#else
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IMX6_BMODE_RESERVED,
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IMX6_BMODE_SATA,
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#endif
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IMX6_BMODE_SERIAL_ROM,
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IMX6_BMODE_SD,
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IMX6_BMODE_ESD,
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IMX6_BMODE_MMC,
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IMX6_BMODE_EMMC,
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IMX6_BMODE_NAND_MIN,
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IMX6_BMODE_NAND_MAX = 0xf,
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};
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static inline u8 imx6_is_bmode_from_gpr9(void)
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{
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return readl(&src_base->gpr10) & IMX6_SRC_GPR10_BMODE;
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}
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u32 imx6_src_get_boot_mode(void);
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void gpr_init(void);
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#endif /* CONFIG_MX6 */
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u32 get_nr_cpus(void);
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u32 get_cpu_rev(void);
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u32 get_cpu_speed_grade_hz(void);
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u32 get_cpu_temp_grade(int *minc, int *maxc);
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const char *get_imx_type(u32 imxtype);
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u32 imx_ddr_size(void);
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void sdelay(unsigned long);
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void set_chipselect_size(int const);
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void init_aips(void);
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void init_src(void);
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void init_snvs(void);
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void imx_wdog_disable_powerdown(void);
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int board_mmc_get_env_dev(int devno);
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int nxp_board_rev(void);
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char nxp_board_rev_string(void);
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/*
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* Initializes on-chip ethernet controllers.
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* to override, implement board_eth_init()
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*/
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int fecmxc_initialize(bd_t *bis);
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u32 get_ahb_clk(void);
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u32 get_periph_clk(void);
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void lcdif_power_down(void);
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int mxs_reset_block(struct mxs_register_32 *reg);
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int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout);
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int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
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unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
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unsigned long reg1, unsigned long reg2);
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#endif
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